TI-radar AWR1843 C674x DSP core
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device_cfg.h
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#ifndef DEVICE_CFG_H
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#define DEVICE_CFG_H
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/* Tx Channel Configuration */
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#define TX_CHANNEL_1_ENABLE (1U << 0U)
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#define TX_CHANNEL_2_ENABLE (1U << 1U)
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#define TX_CHANNEL_3_ENABLE (1U << 2U)
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#define TX_CHANNEL_1_2_ENABLE (TX_CHANNEL_1_ENABLE | TX_CHANNEL_2_ENABLE)
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#define TX_CHANNEL_2_3_ENABLE (TX_CHANNEL_2_ENABLE | TX_CHANNEL_3_ENABLE)
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#define TX_CHANNEL_1_3_ENABLE (TX_CHANNEL_1_ENABLE | TX_CHANNEL_3_ENABLE)
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#define TX_CHANNEL_1_2_3_ENABLE (TX_CHANNEL_1_ENABLE | TX_CHANNEL_2_ENABLE | TX_CHANNEL_3_ENABLE)
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/* Rx Channel Configuration */
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#define RX_CHANNEL_1_ENABLE (1U << 0U)
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#define RX_CHANNEL_2_ENABLE (1U << 1U)
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#define RX_CHANNEL_3_ENABLE (1U << 2U)
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#define RX_CHANNEL_4_ENABLE (1U << 3U)
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#define RX_CHANNEL_1_2_ENABLE (RX_CHANNEL_1_ENABLE | RX_CHANNEL_2_ENABLE)
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#define RX_CHANNEL_1_3_ENABLE (RX_CHANNEL_1_ENABLE | RX_CHANNEL_3_ENABLE)
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#define RX_CHANNEL_1_4_ENABLE (RX_CHANNEL_1_ENABLE | RX_CHANNEL_4_ENABLE)
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#define RX_CHANNEL_2_3_ENABLE (RX_CHANNEL_2_ENABLE | RX_CHANNEL_3_ENABLE)
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#define RX_CHANNEL_2_4_ENABLE (RX_CHANNEL_2_ENABLE | RX_CHANNEL_4_ENABLE)
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#define RX_CHANNEL_3_4_ENABLE (RX_CHANNEL_3_ENABLE | RX_CHANNEL_4_ENABLE)
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#define RX_CHANNEL_1_2_3_ENABLE (RX_CHANNEL_1_ENABLE | RX_CHANNEL_2_ENABLE | RX_CHANNEL_3_ENABLE)
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#define RX_CHANNEL_2_3_4_ENABLE (RX_CHANNEL_2_ENABLE | RX_CHANNEL_3_ENABLE | RX_CHANNEL_4_ENABLE)
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#define RX_CHANNEL_1_3_4_ENABLE (RX_CHANNEL_1_ENABLE | RX_CHANNEL_3_ENABLE | RX_CHANNEL_4_ENABLE)
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#define RX_CHANNEL_1_2_3_4_ENABLE (RX_CHANNEL_1_ENABLE | RX_CHANNEL_2_ENABLE | RX_CHANNEL_3_ENABLE | RX_CHANNEL_4_ENABLE)
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/* ADC Config Settings */
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#define ADC_BITS_12 (0U)
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#define ADC_BITS_14 (1U)
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#define ADC_BITS_16 (2U)
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#define ADC_FORMAT_REAL (0U)
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#define ADC_FORMAT_COMPLEX (1U)
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#define ADC_FORMAT_CPMLEX_WITH_IMG_BAND (2U)
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#define ADC_I_FIRST (0U)
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#define ADC_Q_FIRST (1U)
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#define ADC_INTERLEAVED_MODE (0U)
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#define ADC_NON_INTERLEAVED_MODE (1U)
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/* Data Path Configuration */
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#define DATA_PATH_CSI2 (0U)
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#define DATA_PATH_LVDS (1U)
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#define DATA_PATH_FMT1_SUPRESS (0U)
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#define DATA_PATH_FMT1_CP_CQ (1U)
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#define DATA_PATH_FMT1_CQ_CP (2U)
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#define DATA_PATH_FMT0_ADC_DATA_ONLY (0U)
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#define DATA_PATH_FMT0_CP_ADC_DATA (1U)
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#define DATA_PATH_FMT0_ADC_CP_DATA (2U)
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#define DATA_PATH_FMT0_CP_ADC_CQ_DATA (3U)
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#define DATA_PATH_CQ_FMT_BITS_12 (0U)
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#define DATA_PATH_CQ_FMT_BITS_14 (1U)
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#define DATA_PATH_CQ_FMT_BITS_16 (2U)
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/* LVDS Clock Configuration */
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#define LVDS_LANE_CLOCK_SDR (0U)
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#define LVDS_LANE_CLOCK_DDR (1U)
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#define LVDS_ALL_LANE_EN (0xFU)
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#define LVDS_DATA_RATE_900 (0U)
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#define LVDS_DATA_RATE_600 (1U)
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#define LVDS_DATA_RATE_450 (2U)
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#define LVDS_DATA_RATE_400 (3U)
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#define LVDS_DATA_RATE_300 (4U)
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#define LVDS_DATA_RATE_225 (5U)
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#define LVDS_DATA_RATE_150 (6U)
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/* LCDS Lane Configuration */
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#define LVDS_LANE1_DISABLE (0U)
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#define LVDS_LANE1_FORMAT_0 (1U)
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#define LVDS_LANE1_FORMAT_1 (2U)
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#define LVDS_LANE2_DISABLE (0U)
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#define LVDS_LANE2_FORMAT_0 (1U)
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#define LVDS_LANE2_FORMAT_1 (2U)
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#define LVDS_LANE3_DISABLE (0U)
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#define LVDS_LANE3_FORMAT_0 (1U)
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#define LVDS_LANE3_FORMAT_1 (2U)
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#define LVDS_LANE4_DISABLE (0U)
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#define LVDS_LANE4_FORMAT_0 (1U)
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#define LVDS_LANE4_FORMAT_1 (2U)
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#define LVDS_LANE_MSB_FIRST_ENABLE (1U)
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#define LVDS_LANE_MSB_FIRST_DISABLE (0U)
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#define LVDS_LANE_PACKET_END_PULSE_ENABLE (1U)
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#define LVDS_LANE_PACKET_END_PULSE_DISABLE (0U)
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#define LVDS_LANE_CRC_ENABLE (1U)
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#define LVDS_LANE_CRC_DISABLE (0U)
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#define LVDS_LANE_TI_MODE_ENABLE (1U)
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#define LVDS_LANE_TI_MODE_DISABLE (0U)
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/* Advanced configuration */
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#define ANA_CHANNEL_COMPLEX_CHAIN (0U)
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#define ANA_CHANNEL_REAL_CHAIN (1U)
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#define LP_ADC_MODE_REGULAR (0U)
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#define LP_ADC_MODE_LOW_POWER (1U)
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#define NOISE_FIGURE_LOW (0U)
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#define NOISE_FIGURE_HIGH (1U)
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/* CHIRP Profile Settings */
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#define CHIRP_HPF1_CORNER_FREQ_175K (0U)
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#define CHIRP_HPF1_CORNER_FREQ_235K (1U)
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#define CHIRP_HPF1_CORNER_FREQ_350K (2U)
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#define CHIRP_HPF1_CORNER_FREQ_700K (3U)
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#define CHIRP_HPF2_CORNER_FREQ_350K (0U)
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#define CHIRP_HPF2_CORNER_FREQ_700K (1U)
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#define CHIRP_HPF2_CORNER_FREQ_1_4M (2U)
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#define CHIRP_HPF2_CORNER_FREQ_2_8M (3U)
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#define CHIRP_HPF2_CORNER_FREQ_5M (4U)
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#define CHIRP_HPF2_CORNER_FREQ_7_5M (5U)
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#define CHIRP_HPF2_CORNER_FREQ_10M (6U)
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#define CHIRP_HPF2_CORNER_FREQ_15M (7U)
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/* Some MACROS to simplify programming the device */
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#define ROUND_TO_INT32(X) ((int32_t) (X))
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#define CONV_FREQ_GHZ_TO_CODEWORD(X) ROUND_TO_INT32(X * (1.0e9/53.644))
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#define CONV_SLOPE_MHZ_PER_US_TO_CODEWORD(X) (ROUND_TO_INT32(X * (1000.0/48.279)))
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#define LOG2_APPROX(X) ((X <= 1)? 0:((X <= 2)? 1:((X <= 4)? 2:((X <= 8)? 3:((X <= 16)? 4:((X <= 32)? 5:((X <= 64)? 6:((X <= 128)? 7:((X <= 256)? 8:((X <= 512)? 9:((X <= 1024)? 10:11)))))))))))
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#define SPEED_OF_LIGHT_IN_METERS_PER_SEC (3.0e8)
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#define SPEED_OF_LIGHT_IN_METERS_PER_USEC (3.0e2)
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#endif
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common
device_cfg.h
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