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Chirp row configuration, radarSS stores each chirp config in memory in 3 rows. More...
#include <control/mmwavelink/include/rl_sensor.h>
Data Fields | |
| rlUInt32_t | chirpNR1 |
| Nth Chirp config Row 1 Bits Definition 3:0 PROFILE_INDX Valid range 0 to 3 7:4 RESERVED 13:8 FREQ_SLOPE_VAR For 77GHz Devices (76GHz to 81GHz): 1 LSB = 3.6e9*900 /2^26 ~48.279kHz Valid range: 0 to 63 For 60GHz Devices (57GHz to 64GHz): 1 LSB = 2.7e9*900 /2^26 ~36.21kHz Valid range: 0 to 63 15:14 RESERVED 18:16 TX_ENABLE Bit Definition b0 TX0 Enable b1 TX1 Enable b2 TX2 Enable 23:19 RESERVED 29:24 BPM_CONSTANT_BITS Bit Definition b0 CONST_BPM_VAL_TX0_OFF Value of Binary Phase Shift value for TX0, when during idle time b1 CONST_BPM_VAL_TX0_ON Value of Binary Phase Shift value for TX0, during chirp b2 CONST_BPM_VAL_TX1_OFF For TX1 b3 CONST_BPM_VAL_TX1_ON For TX1 b4 CONST_BPM_VAL_TX2_OFF For TX2 b5 CONST_BPM_VAL_TX2_ON For TX2 31:30 RESERVED. | |
| rlUInt32_t | chirpNR2 |
| Nth Chirp config Row 2 Bits Definition b22:0 FREQ_START_VAR 1 LSB = 3.6e9/2^26 ~53.644kHz Valid range: 0 to 8388607 b31:23 RESERVED. | |
| rlUInt32_t | chirpNR3 |
| Nth Chirp config Row 3 Bits Definition b11:0 IDLE_TIME_VAR 1 LSB = 10 ns Valid range: 0 to 4095 b15:12 RESERVED b27:16 ADC_START_TIME_VAR 1 LSB = 10 ns Valid range: 0 to 4095 b31:28 RESERVED. | |
Chirp row configuration, radarSS stores each chirp config in memory in 3 rows.
Definition at line 3300 of file rl_sensor.h.