EDMA external driver interface. More...

#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
#include <ti/common/mmwave_error.h>
#include <ti/drivers/edma/include/edma_low_level.h>

Data Structures
struct	EDMA_errorInfo_t_
	Error Information structure. Information is from EMR(H), QEMR, CCERR registers as per EDMA UG. More...

struct	EDMA_transferControllerBusErrorInfo_t_
	Transfer controller bus error information, relevant when EDMA_transferControllerErrorInfo_t_::isBusError is true. More...

struct	EDMA_transferControllerErrorInfo_t_
	Transfer controller error information. More...

struct	EDMA_paramSetConfig_t_
	PaRAM Set configuration. More...

struct	EDMA_channelConfig_t_
	Channel configuration. Specifies the full configuration for a DMA or QDMA channel with associated paramId and param Set configuration. More...

struct	EDMA_paramConfig_t_
	Param configuration typically used for stand-alone param sets (param sets not associated with any of the 64 DMA channels) such as for QDMA channels or for linking purposes. More...

struct	EDMA_transferControllerErrorConfig_t_
	Error configuration for a transfer controller, allows enabling/disabling of various error conditions. More...

struct	EDMA_errorConfig_t_
	Error configuration for transfer controller, allows enabling/disabling of various error conditions. More...

struct	EDMA_queueEntryInfo_t_
	Queue entry information. More...

struct	EDMA_queueStatusInfo_t_
	Queue status information. More...

struct	EDMA_statusInfo_t_
	EDMA status information at the time of querying status using EDMA_getStatusInfo. This is not some software state but it is hardware state, typically used for debugging purposes. Note CCSTAT::QUEACTVx bits are not reported because they are redundant information given the EDMA_queueStatusInfo_t_. More...

struct	EDMA_performanceConfig_t_
	EDMA performance configuration. More...

struct	EDMA_instanceInfo_t_
	EDMA instance properties information. More...

Macros
#define	EDMA_NUM_DMA_CHANNELS (64U)
	Total number of DMA channels.

#define	EDMA_NUM_TCC ((uint8_t)64)
	Total number of transfer completion codes.

#define	EDMA_NUM_QDMA_CHANNELS ((uint8_t)8)
	Total number of QDMA channels.

#define	EDMA_MAX_NUM_EVENT_QUEUES ((uint8_t)8)
	Maximum number of event queues in any EDMA IP.

#define	EDMA_MAX_NUM_TRANSFER_CONTROLLERS (EDMA_MAX_NUM_EVENT_QUEUES)
	Maximum number of transfer controllers in any EDMA IP.

#define	EDMA_NUM_QUEUE_ENTRIES ((uint8_t)16)
	Number of entries in each queue in any EDMA IP.

#define	EDMA_QDMA_TRIG_WORD_OFFSET_OPT (0U)
	Set the OPT field (Offset Address 0h Bytes) as the QDMA trigger word.

#define	EDMA_QDMA_TRIG_WORD_OFFSET_SRC (1U)
	Set the SRC field (Offset Address 4h Bytes) as the QDMA trigger word.

#define	EDMA_QDMA_TRIG_WORD_OFFSET_ACNT_BCNT (2U)
	Set the (ACNT + BCNT) field (Offset Address 8h Bytes) as the QDMA trigger word.

#define	EDMA_QDMA_TRIG_WORD_OFFSET_DST (3U)
	Set the DST field (Offset Address Ch Bytes) as the QDMA trigger word.

#define	EDMA_QDMA_TRIG_WORD_OFFSET_SRC_DST_BIDX (4U)
	Set the (SRCBIDX + DSTBIDX) field (Offset Address 10h Bytes) as the QDMA trigger word.

#define	EDMA_QDMA_TRIG_WORD_OFFSET_LINK_BCNTRLD (5U)
	Set the (LINK + BCNTRLD) field (Offset Address 14h Bytes) as the QDMA trigger word.

#define	EDMA_QDMA_TRIG_WORD_OFFSET_SRC_DST_CIDX (6U)
	Set the (SRCCIDX + DSTCIDX) field (Offset Address 18h Bytes) as the QDMA trigger word.

#define	EDMA_QDMA_TRIG_WORD_OFFSET_CCNT (7U)
	Set the (CCNT + RSVD) field (Offset Address 1Ch Bytes) as the QDMA trigger word.

#define	EDMA_QDMA_TRIG_WORD_OFFSET_DEFAULT (EDMA_QDMA_TRIG_WORD_OFFSET_CCNT)
	Default Trigger Word is CCNT.

#define	EDMA_NULL_LINK_ADDRESS 0xFFFFU
	NULL Link Address.

#define	EDMA_E_INVALID__HANDLE_NULL (MMWAVE_ERRNO_EDMA_BASE-0)
	Handle argument is NULL pointer.

#define	EDMA_E_INVALID__CONFIG_POINTER_NULL (MMWAVE_ERRNO_EDMA_BASE-1)
	Config argument is NULL pointer.

#define	EDMA_E_INVALID__DMA_CHANNEL_TYPE (MMWAVE_ERRNO_EDMA_BASE-2)
	Config's channelType is invalid.

#define	EDMA_E_INVALID__DMA_CHANNEL_ID (MMWAVE_ERRNO_EDMA_BASE-3)
	Config's channelId out of range.

#define	EDMA_E_INVALID__PARAM_ID (MMWAVE_ERRNO_EDMA_BASE-4)
	Config's paramId out of range.

#define	EDMA_E_INVALID__EVENT_QUEUE_ID (MMWAVE_ERRNO_EDMA_BASE-5)
	Config's eventQueueId out of range.

#define	EDMA_E_INVALID__TRNSFR_COMPLETION_PARAMS (MMWAVE_ERRNO_EDMA_BASE-6)
	Config's both interrupt completion flags are false but transfer completion call back function is configured (non NULL).

#define	EDMA_E_INVALID__TRANSFER_COMPLETION_CODE (MMWAVE_ERRNO_EDMA_BASE-7)
	Config's transferCompletionCode is invalid.

#define	EDMA_E_INVALID__TRANSFER_TYPE (MMWAVE_ERRNO_EDMA_BASE-8)
	Config's transferType is invalid.

#define	EDMA_E_INVALID__QDMA_CHANNEL_ID (MMWAVE_ERRNO_EDMA_BASE-9)
	Invalid Qdma channelId.

#define	EDMA_E_INVALID__INSTANCE_ID (MMWAVE_ERRNO_EDMA_BASE-10)
	Invalid Instance Id during open.

#define	EDMA_E_INVALID__QDMA_TRIGGER_WORD (MMWAVE_ERRNO_EDMA_BASE-11)
	Invalid QDMA trigger word.

#define	EDMA_E_INVALID__TRANSFER_CONTROLLER_ID (MMWAVE_ERRNO_EDMA_BASE-12)
	Invalid transfer controller Id.

#define	EDMA_E_INVALID__TRANSFER_CONTROLLER_READ_RATE (MMWAVE_ERRNO_EDMA_BASE-13)
	Invalid transfer controller read rate.

#define	EDMA_E_INVALID__QUEUE_PRIORITY (MMWAVE_ERRNO_EDMA_BASE-14)
	Invalid queue priority in performance config.

#define	EDMA_E_INVALID__EVENT_QUEUE_THRESHOLD (MMWAVE_ERRNO_EDMA_BASE-15)
	During EDMA_startTransfer, unexpected QDMA miss event detected.

#define	EDMA_E_INVALID__PARAM_ID_NOT_SAME_AS_CHANNEL_ID (MMWAVE_ERRNO_EDMA_BASE-16)
	During EDMA_configChannel, param ID must be same as channel ID for DMA channel because channel mapping does not exist in the hardware.

#define	EDMA_E_INVALID__STATUS_POINTER_NULL (MMWAVE_ERRNO_EDMA_BASE-17)
	Status argument is NULL pointer.

#define	EDMA_E_INVALID__INSTANCEINFO_POINTER_NULL (MMWAVE_ERRNO_EDMA_BASE-18)
	InstanceInfo argument is NULL pointer.

#define	EDMA_E_UNEXPECTED__DMA_EVENT_MISS_DETECTED (MMWAVE_ERRNO_EDMA_BASE-25)
	During EDMA_startTransfer, unexpected DMA miss event detected.

#define	EDMA_E_UNEXPECTED__QDMA_EVENT_MISS_DETECTED (MMWAVE_ERRNO_EDMA_BASE-26)
	During EDMA_startTransfer, unexpected QDMA miss event detected.

#define	EDMA_E_UNEXPECTED__EDMA_INSTANCE_REOPEN (MMWAVE_ERRNO_EDMA_BASE-27)
	Attempt to reopen and already opened instance.

#define	EDMA_E_UNEXPECTED__ATTEMPT_TO_TEST_COMPLETION (MMWAVE_ERRNO_EDMA_BASE-28)
	Attempt to issue EDMA_isTransferComplete despite non-NULL completion call-back function.

#define	EDMA_E_OSAL__HWIP_CREATE_TRANSFER_COMPLETION_ISR_RETURNED_NULL (MMWAVE_ERRNO_EDMA_BASE-40)
	HwiP_create returned NULL on transfer completion Isr creation.

#define	EDMA_E_OSAL__HWIP_CREATE_ERROR_ISR_RETURNED_NULL (MMWAVE_ERRNO_EDMA_BASE-41)
	HwiP_create returned NULL on CC error Isr creation.

#define	EDMA_E_OSAL__HWIP_CREATE_TRANSFER_CONTROLLER_ERROR_ISRS_RETURNED_NULL (MMWAVE_ERRNO_EDMA_BASE-42)
	HwiP_create returned NULL on one of transfer controller error Isrs creation.

#define	EDMA_E_OSAL__HWIP_DELETE_TRANSFER_COMPLETION_ISR_ERROR (MMWAVE_ERRNO_EDMA_BASE-43)
	HwiP_delete returned NULL on transfer completion Isr deletion.

#define	EDMA_E_OSAL__HWIP_DELETE_ERROR_ISR_ERROR (MMWAVE_ERRNO_EDMA_BASE-44)
	HwiP_delete returned NULL on CC error Isr deletion.

#define	EDMA_E_OSAL__HWIP_DELETE_TRANSFER_CONTROLLER_ERROR_ISRS_ERROR (MMWAVE_ERRNO_EDMA_BASE-45)
	HwiP_delete returned NULL on one of transfer controller error Isrs deletion.

#define	EDMA_E_INUSE (MMWAVE_ERRNO_EDMA_BASE-60)
	Operation cannot be implemented because a previous operation is still not complete.

#define	EDMA_E_NOTIMPL (MMWAVE_ERRNO_EDMA_BASE-80)
	Operation is not implemented.

#define	EDMA_NO_ERROR ((int32_t)0)
	No Error.

#define	EDMA_EVENT_QUEUE_THRESHOLDING_DISABLED (0x11U)
	Disable thresholding.

#define	EDMA_EVENT_QUEUE_THRESHOLD_QUEUE_EVER_USED (0U)
	Queue ever used i.e queue had non-zero occupancy ever.

#define	EDMA_EVENT_QUEUE_THRESHOLD_QUEUE_EVER_FULL (0x10U)
	Queue ever full i.e was there ever a time when queue was full.

#define	EDMA_EVENT_QUEUE_THRESHOLD_MAX (EDMA_EVENT_QUEUE_THRESHOLD_QUEUE_EVER_FULL)
	Max queue threshold, same as queue ever full.

#define	EDMA_READ_RATE_AS_FAST_AS_POSSIBLE (EDMA_TC_RDRATE_RDRATE_AFAP)
	as fast as possible

#define	EDMA_READ_RATE_EVERY_4_CYCLES (EDMA_TC_RDRATE_RDRATE_READEVERY4CYCLES)
	4 cycles between reads

#define	EDMA_READ_RATE_EVERY_8_CYCLES (EDMA_TC_RDRATE_RDRATE_READEVERY8CYCLES)
	8 cycles between reads

#define	EDMA_READ_RATE_EVERY_16_CYCLES (EDMA_TC_RDRATE_RDRATE_READEVERY16CYCLES)
	16 cycles between reads

#define	EDMA_READ_RATE_EVERY_32_CYCLES (EDMA_TC_RDRATE_RDRATE_READEVERY32CYCLES)
	32 cycles between reads

Typedefs
typedef void *	EDMA_Handle
	A handle that is returned from a EDMA_open call.

typedef void(*	EDMA_transferCompletionCallbackFxn_t) (uintptr_t arg, uint8_t transferCompletionCode)
	Transfer completion call back function definition. More...

typedef struct EDMA_errorInfo_t_	EDMA_errorInfo_t
	Error Information structure. Information is from EMR(H), QEMR, CCERR registers as per EDMA UG.

typedef void(*	EDMA_errorCallbackFxn_t) (EDMA_Handle handle, EDMA_errorInfo_t *errorInfo)
	Error call back function. More...

typedef struct EDMA_transferControllerBusErrorInfo_t_	EDMA_transferControllerBusErrorInfo_t
	Transfer controller bus error information, relevant when EDMA_transferControllerErrorInfo_t_::isBusError is true.

typedef struct EDMA_transferControllerErrorInfo_t_	EDMA_transferControllerErrorInfo_t
	Transfer controller error information.

typedef void(*	edmaTransferControllerErrorCallbackFxn_t) (EDMA_Handle handle, EDMA_transferControllerErrorInfo_t *errorInfo)
	Transfer controller error call back function. Usually transfer controller errors are fatal. More...

typedef struct EDMA_paramSetConfig_t_	EDMA_paramSetConfig_t
	PaRAM Set configuration.

typedef struct EDMA_channelConfig_t_	EDMA_channelConfig_t
	Channel configuration. Specifies the full configuration for a DMA or QDMA channel with associated paramId and param Set configuration.

typedef struct EDMA_paramConfig_t_	EDMA_paramConfig_t
	Param configuration typically used for stand-alone param sets (param sets not associated with any of the 64 DMA channels) such as for QDMA channels or for linking purposes.

typedef struct EDMA_transferControllerErrorConfig_t_	EDMA_transferControllerErrorConfig_t
	Error configuration for a transfer controller, allows enabling/disabling of various error conditions.

typedef struct EDMA_errorConfig_t_	EDMA_errorConfig_t
	Error configuration for transfer controller, allows enabling/disabling of various error conditions.

typedef struct EDMA_queueEntryInfo_t_	EDMA_queueEntryInfo_t
	Queue entry information.

typedef struct EDMA_queueStatusInfo_t_	EDMA_queueStatusInfo_t
	Queue status information.

typedef struct EDMA_statusInfo_t_	EDMA_statusInfo_t
	EDMA status information at the time of querying status using EDMA_getStatusInfo. This is not some software state but it is hardware state, typically used for debugging purposes. Note CCSTAT::QUEACTVx bits are not reported because they are redundant information given the EDMA_queueStatusInfo_t_.

typedef struct EDMA_performanceConfig_t_	EDMA_performanceConfig_t
	EDMA performance configuration.

typedef struct EDMA_instanceInfo_t_	EDMA_instanceInfo_t
	EDMA instance properties information.

Functions
int32_t	EDMA_configChannel (EDMA_Handle handle, EDMA_channelConfig_t const *config, bool isEnableChannel)

int32_t	EDMA_enableChannel (EDMA_Handle handle, uint8_t channelId, uint8_t channelType)

int32_t	EDMA_disableChannel (EDMA_Handle handle, uint8_t channelId, uint8_t channelType)

int32_t	EDMA_chainChannels (EDMA_Handle handle, uint16_t fromParamId, uint8_t toChannelId)

int32_t	EDMA_configParamSet (EDMA_Handle handle, uint16_t paramId, EDMA_paramConfig_t const *config)

int32_t	EDMA_linkParamSets (EDMA_Handle handle, uint16_t fromParamId, uint16_t toParamId)

int32_t	EDMA_startTransfer (EDMA_Handle handle, uint8_t channelId, uint8_t channelType)

int32_t	EDMA_startDmaTransfer (EDMA_Handle handle, uint8_t channelId)

int32_t	EDMA_startQdmaTransfer (EDMA_Handle handle, uint8_t channelId)

int32_t	EDMA_startFinalQdmaTransfer (EDMA_Handle handle, uint8_t channelId)

int32_t	EDMA_isTransferComplete (EDMA_Handle handle, uint8_t transferCompletionCode, bool *isTransferComplete)

int32_t	EDMA_setDestinationAddress (EDMA_Handle handle, uint16_t paramId, uint32_t destinationAddress)

int32_t	EDMA_setSourceAddress (EDMA_Handle handle, uint16_t paramId, uint32_t sourceAddress)

int32_t	EDMA_configErrorMonitoring (EDMA_Handle handle, EDMA_errorConfig_t const *config)

int32_t	EDMA_getErrorStatus (EDMA_Handle handle, bool isAnyError, EDMA_errorInfo_t errorInfo)

int32_t	EDMA_getTransferControllerErrorStatus (EDMA_Handle handle, uint8_t transferControllerId, bool isAnyError, EDMA_transferControllerErrorInfo_t errorInfo)

int32_t	EDMA_getStatusInfo (EDMA_Handle handle, EDMA_statusInfo_t *status)

int32_t	EDMA_configPerformance (EDMA_Handle handle, EDMA_performanceConfig_t const *config)

EDMA_Handle	EDMA_open (uint8_t instanceId, int32_t errorCode, EDMA_instanceInfo_t instanceInfo)

int32_t	EDMA_close (EDMA_Handle handle)

uint8_t	EDMA_getNumInstances (void)

int32_t	EDMA_init (uint8_t instanceId)

Detailed Description

EDMA external driver interface.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
Neither the name of Texas Instruments Incorporated nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Typedef Documentation

typedef void(* EDMA_errorCallbackFxn_t) (EDMA_Handle handle, EDMA_errorInfo_t *errorInfo)

Error call back function.

Parameters

[out]	handle	Handle to the EDMA instance obtained through call to EDMA_open.
[out]	errorInfo	Pointer to error information EDMA_errorInfo_t_.

typedef void(* EDMA_transferCompletionCallbackFxn_t) (uintptr_t arg, uint8_t transferCompletionCode)

Transfer completion call back function definition.

Parameters

[out]	Argument	that was registered during call back registeration during configuration. Handle to the EDMA instance obtained through call to EDMA_open.
[out]	transferCompletionCode	Transfer completion code of the completed transfer.

typedef void(* edmaTransferControllerErrorCallbackFxn_t) (EDMA_Handle handle, EDMA_transferControllerErrorInfo_t *errorInfo)

Transfer controller error call back function. Usually transfer controller errors are fatal.

Parameters

[out]	handle	Handle to the EDMA instance obtained through call to EDMA_open.
[out]	errorInfo	Pointer to error information EDMA_transferControllerErrorInfo_t_.

Data Structures

Macros

Typedefs

Functions

Detailed Description

Typedef Documentation