mmwavelink.h
1 /*************************************************************************************************
2  * FileName : mmwavelink.h
3  *
4  * Description : This file includes all the header files which needs to be included by application
5  *
6  *************************************************************************************************
7  * (C) Copyright 2014, Texas Instruments Incorporated. - TI web address www.ti.com
8  *------------------------------------------------------------------------------------------------
9  *
10  * Redistribution and use in source and binary forms, with or without modification, are permitted
11  * provided that the following conditions are met:
12  *
13  * Redistributions of source code must retain the above copyright notice, this list of
14  * conditions and the following disclaimer.
15  *
16  * Redistributions in binary form must reproduce the above copyright notice, this list of
17  * conditions and the following disclaimer in the documentation and/or other materials provided
18  * with the distribution.
19  *
20  * Neither the name of Texas Instruments Incorporated nor the names of its contributors may be
21  * used to endorse or promote products derived from this software without specific prior
22  * written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
25  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
26  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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35 
36 /*************************************************************************************************
37  * FILE INCLUSION PROTECTION
38  *************************************************************************************************
39  */
40 #ifndef MMWAVELINK_H
41 #define MMWAVELINK_H
42 /*LDRA_NOANALYSIS*/
279 /*LDRA_ANALYSIS*/
280 
281  /****************************************************************************************
282  * INCLUDE FILES
283  *****************************************************************************************
284  */
285 #include <stdint.h>
286 #include <ti/control/mmwavelink/include/rl_datatypes.h>
287 
288 #ifdef __cplusplus
289 extern "C" {
290 #endif
291 
292 /*****************************************************************************************
293  * MACRO DEFINITIONS
294  *****************************************************************************************
295  */
296 
297 /* Export Macro for DLL */
298 #if defined(WIN32) || defined(WIN32_) || defined(_MSC_VER)
299 #define MMWL_EXPORT __declspec(dllexport)
300 #else
301 #define MMWL_EXPORT
302 #endif
303 
305 #define RL_MMWAVELINK_VERSION "1.2.0.1.24.9.18"
306 #define RL_MMWAVELINK_VERSION_MAJOR (1U)
307 #define RL_MMWAVELINK_VERSION_MINOR (2U)
308 #define RL_MMWAVELINK_VERSION_BUILD (0U)
309 #define RL_MMWAVELINK_VERSION_DEBUG (1U)
310 #define RL_MMWAVELINK_VERSION_DAY (24U)
311 #define RL_MMWAVELINK_VERSION_MONTH (9U)
312 #define RL_MMWAVELINK_VERSION_YEAR (18U)
313 
315 #define RL_RET_CODE_OK ((rlReturnVal_t)0) /* no-error */
316 #define RL_RET_CODE_PROTOCOL_ERROR (-1) /* mmWaveLink Protocol error */
317 #define RL_RET_CODE_INVALID_INPUT (-2) /* invalid input from the application */
318 #define RL_RET_CODE_SELF_ERROR (-3) /* error in mmWaveLink itself */
319 #define RL_RET_CODE_RADAR_IF_ERROR (-4) /* Radar HW/SW interface error */
320 #define RL_RET_CODE_MALLOC_ERROR (-5) /* memory allocation error */
321 #define RL_RET_CODE_CRC_FAILED (-6) /* CRC value mismatched wrt
322  received data */
323 #define RL_RET_CODE_CHKSUM_FAILED (-7) /* Checksum value mismatched wrt to
324  received data */
325 #define RL_RET_CODE_RESP_TIMEOUT (-8) /* device failed to send response
326  within time */
327 #define RL_RET_CODE_FATAL_ERROR (-9) /* Fatal error internal to
328  mmWaveLink APIs */
329 #define RL_RET_CODE_RADAR_OSIF_ERROR (-10) /* OS interface failure */
330 #define RL_RET_CODE_INVALID_STATE_ERROR (-11) /* Invalid state within mmWaveLink */
331 #define RL_RET_CODE_API_NOT_SUPPORTED (-12) /* API called is not supported */
332 #define RL_RET_CODE_MSGID_MISMATCHED (-13) /* Message-ID mismatched in
333  response data */
334 #define RL_RET_CODE_NULL_PTR (-14) /* Null pointer error */
335 #define RL_RET_CODE_INTERFACE_CB_NULL (-15) /* Interface callback passed as NULL */
336 
338 #define RL_RET_CODE_INVLD_OPCODE (1U) /* Incorrect opcode/Msg ID */
339 #define RL_RET_CODE_INVLD_NUM_SB (2U) /* Incorrect no. of Sub-Block */
340 #define RL_RET_CODE_INVLD_SB_ID (3U) /* Incorrect Sub-Block ID */
341 #define RL_RET_CODE_INVLD_SB_LEN (4U) /* Incorrect Sub-Block Length */
342 #define RL_RET_CODE_SB_INVL_DATA (5U) /* Incorrect Sub-Block Data */
343 #define RL_RET_CODE_SB_PROCESS_ERR (6U) /* Error in Sub Block processing */
344 #define RL_RET_CODE_MISMATCH_FILE_CRC (7U) /* Mismatch in File CRC */
345 #define RL_RET_CODE_MISMATCH_FILE_TYPE (8U) /* Mismatch in File Type */
346 
348 #define RL_RET_CODE_FRAME_ALREADY_STARTED (20U) /* Frames are already started when the
349  FRAME_START command was issued */
350 #define RL_RET_CODE_FRAME_ALREADY_ENDED (21U) /* Frames are already stopped when the
351  FRAME_STOP command was issued */
352 #define RL_RET_CODE_FRAME_CFG_NOT_RECVD (22U) /* No valid frame configuration API was
353  issued and frames are started */
354 #define RL_RET_CODE_FRAME_TRIG_INVL_IN (23U) /* START_STOP_CMD parameter is out of
355  range*/
356 
358 #define RL_RET_CODE_CH_CFG_RX_INVAL_IN (24U) /* RX_CHAN_EN parameter is out of range
359  may vary based on device */
360 #define RL_RET_CODE_CH_CFG_TX_INVAL_IN (25U) /* TX_CHAN_EN parameter is out of range
361  may vary based on device */
362 #define RL_RET_CODE_CH_CFG_CASC_INVAL_IN (26U) /* CASCADING_CFG parameter is out of
363  range [0, 2] */
364 
366 #define RL_RET_CODE_ADC_BITS_INVAL_IN (27U) /* NUM_ADC_BITS parameter is out of
367  range [0, 2] */
368 #define RL_RET_CODE_ADC_FORM_INVAL_IN (28U) /* ADC_OUT_FMT parameter is out of
369  range [0, 3] */
370 
372 #define RL_RET_CODE_LP_ADC_INVAL_IN (29U) /* LP_ADC_MODE parameter is out of
373  range [0, 1] */
374 
376 #define RL_RET_CODE_DYN_PS_INVAL_IN (30U) /* BLOCK_CFG parameter is out of
377  range [0, 7] */
378 
380 #define RL_RET_CODE_HSI_DIV_INVAL_IN (31U) /* HSI clock rate code[1:0] is 0 */
381 #define RL_RET_CODE_RESERVED0 (32U)
382 #define RL_RET_CODE_HSI_DIV_INVAL_1IN (33U) /* HSI clock rate code[3:2] is 3 &
383  HSI clock rate code[1:0] is 2 */
384 #define RL_RET_CODE_HSI_DIV_INVAL_2IN (34U) /* HSI clock rate code[3:2] is 3 &
385  HSI clock rate code[1:0] is 2 */
386 
388 #define RL_RET_CODE_PF_IND_INVAL_IN (35U) /* PF indx >= 4 */
389 #define RL_RET_CODE_PF_START_FREQ_INVAL_IN (36U) /* PF freq const is not
390  with[76GHz,81GHz] in limit */
391 #define RL_RET_CODE_PF_IDLE_TIME_INVAL_IN (37U) /* PF idle time const > 5.24ms */
392 #define RL_RET_CODE_PF_IDLE_TIME_1INVAL_IN (38U) /* Maximum DFE spill time >
393  PF idle time const */
394 #define RL_RET_CODE_PF_ADC_START_INVAL_IN (39U) /* PF ADC start time const > 4095 */
395 #define RL_RET_CODE_PF_RAMP_END_INVAL_IN (40U) /* PF ramp end time > 524287 */
396 #define RL_RET_CODE_PF_RAMP_END_1INVAL_IN (41U) /* PF ramp end time < PF ADC start
397  time const + ADC sampling time */
398 #define RL_RET_CODE_PF_TX0_INVAL_IN (42U) /* PF_TX_OUTPUT_POWER_BACKOFF for
399  TX0 > 30 */
400 #define RL_RET_CODE_PF_TX1_INVAL_IN (43U) /* PF_TX_OUTPUT_POWER_BACKOFF for
401  TX1 > 30 */
402 #define RL_RET_CODE_PF_TX2_INVAL_IN (44U) /* PF_TX_OUTPUT_POWER_BACKOFF for
403  TX2 > 30 */
404 #define RL_RET_CODE_RESERVED1 (45U)
405 #define RL_RET_CODE_PF_FREQ_SLOPE_1INVAL_IN (46U) /* Ramp end freq is not
406  with[76GHz,81GHz] in limits */
407 #define RL_RET_CODE_PF_TX_START_INVAL_IN (47U) /* Absolute value of TX_START_TIME
408  is > 38.45us */
409 #define RL_RET_CODE_PF_NUM_ADC_SMAP_INVAL_IN (48U) /* Number of ADC samples is not
410  within [64,8192] */
411 #define RL_RET_CODE_PF_DFE_SAMP_RATE_INVAL_IN (49U) /* Output sampling rate is not
412  within [2, 37.5]Msps */
413 #define RL_RET_CODE_PF_HPF1_CF_INVAL_IN (50U) /* HPF1 corner frequency > 700 kHz */
414 #define RL_RET_CODE_PF_HPF2_CF_INVAL_IN (51U) /* HPF2 corner frequency > 2.8 MHz */
415 #define RL_RET_CODE_PF_RX_GAIN_INVAL_IN (52U) /* PF_RX_GAIN is not within [24, 52] dB
416  orPF_RX_GAIN is an odd number */
417 #define RL_RET_CODE_RESERVED2 (53U)
418 #define RL_RET_CODE_RESERVED3 (54U)
419 #define RL_RET_CODE_RESERVED4 (55U)
420 #define RL_RET_CODE_RESERVED5 (56U)
421 #define RL_RET_CODE_RESERVED6 (57U)
422 #define RL_RET_CODE_RESERVED7 (58U)
423 
425 #define RL_RET_CODE_CHIRP_START_INVAL_IN (59U) /* Chirp Start indx >= 512 */
426 #define RL_RET_CODE_CHIRP_END_INVAL_IN (60U) /* Chirp End indx >= 512 */
427 #define RL_RET_CODE_CHIRP_END_1INVAL_IN (61U) /* Chirp Start indx > Chirp End indx */
428 #define RL_RET_CODE_CHIRP_PF_IND_INVAL_IN (62U) /* PF indx >= 4 */
429 #define RL_RET_CODE_CHIRP_PF_IND_1INVAL_IN (63U) /* PF corresponding to PF indx is not
430  defined */
431 #define RL_RET_CODE_CHIRP_START_FREQ_INVAL_IN (64U) /* Chirp freq start > 8388607 */
432 #define RL_RET_CODE_CHIRP_SLOPE_INVAL_IN (65U) /* Chirp freq slope > 63 */
433 #define RL_RET_CODE_CHIRP_SLOPE_1INVAL_IN (66U) /* Chirp start or end
434  freq[76GHz,81GHz] is outside */
435 #define RL_RET_CODE_CHIRP_IDLE_TIME_INVAL_IN (67U) /* Chirp Idle time > 4095 */
436 #define RL_RET_CODE_CHIRP_ADC_START_INVAL_IN (68U) /* Chirp ADC start time > 4095 */
437 #define RL_RET_CODE_CHIRP_ADC_START_1INVAL_IN (69U) /* Ramp end time < ADC start time +
438  ADC sampling time */
439 #define RL_RET_CODE_CHIRP_TX_ENA_INVAL_IN (70U) /* Chirp TX enable > 7 */
440 #define RL_RET_CODE_CHIRP_TX_ENA_1INVAL_IN (71U) /* Chirp TX enable indicates to enable
441  a TX which is not enabled in
442  Channel config */
443 
445 #define RL_RET_CODE_FRAME_CHIRP_STR_INVAL_IN (72U) /* Chirp Start indx >= 512 */
446 #define RL_RET_CODE_FRAME_CHIRP_END_INVAL_IN (73U) /* Chirp End indx >= 512 */
447 #define RL_RET_CODE_FRAME_CHIRP_END_1INVAL_IN (74U) /* Chirp Start indx > Chirp End indx */
448 #define RL_RET_CODE_FRAME_CHIRP_END_2INVAL_IN (75U) /* Chirp used in frame is not
449  configured by Chirp config */
450 #define RL_RET_CODE_FRAME_CHIRP_PF_INVAL_IN (76U) /* Profile used in frame is not
451  configured by PF config */
452 #define RL_RET_CODE_FRAME_CHIRP_LOOPS_INVAL_IN (77U) /* No. of loops is outside[1,255] */
453 #define RL_RET_CODE_RESERVED8 (78U)
454 #define RL_RET_CODE_FRAME_PERIOD_INVAL_IN (79U) /* Frame periodicity is
455  outside[100us,1.342s] */
456 #define RL_RET_CODE_FRAME_PERIOD_1INVAL_IN (80U) /* Frame ON time < Frame periodicity */
457 #define RL_RET_CODE_FRAME_TRIG_SEL_INVAL_IN (81U) /* Trigger select is outside[1,2] */
458 #define RL_RET_CODE_FRAME_TRIG_DELAY_INVAL_IN (82U) /* Frame Trigger delay > 100us */
459 #define RL_RET_CODE_FRAME_IS_ONGOING (83U) /* API issued when frame is ongoing */
460 
462 #define RL_RET_CODE_AFRAME_NUM_SUBF_INVAL_IN (84U) /* No. Sub Frames is outside[1,4] */
463 #define RL_RET_CODE_AFRAME_FORCE_PF_INVAL_IN (85U) /* Force single Profile is
464  outside[1,4] */
465 #define RL_RET_CODE_AFRAME_PF_IND_INVAL_IN (86U) /* Force single Profile >= 4 */
466 #define RL_RET_CODE_AFRAME_PF_IND_1INVAL_IN (87U) /* Profile defined by Force Single
467  Profile is not defined */
468 #define RL_RET_CODE_AFRAME_CHIRP_STR_INVAL_IN (88U) /* Sub Frame Chirp Start indx >= 512 */
469 #define RL_RET_CODE_AFRAME_NCHIRP_INVAL_IN (89U) /* Sub Frame NO. of unique chirps per
470  Burst is outside[1,512] */
471 #define RL_RET_CODE_AFRAME_NCHIRP_1INVAL_IN (90U) /* Chirp used in frame is not
472  configured by Chirp config */
473 #define RL_RET_CODE_AFRAME_CHIRP_PF_INVAL_IN (91U) /* Profie used in the frame is not
474  configured by profile config */
475 #define RL_RET_CODE_AFRAME_CHIRP_LOOPS_INVAL_IN (92U) /* Sub Frame No. of loops is
476  outside[1,225] */
477 #define RL_RET_CODE_AFRAME_BURST_PERIOD_INVAL_IN (93U) /* Sub Frame burst period is
478  outside[100us,1.342s] */
479 #define RL_RET_CODE_AFRAME_BURST_PER_1INVAL_IN (94U) /* Burst ON time > Burst period */
480 #define RL_RET_CODE_AFRAME_BURST_STIND_INVAL_IN (95U) /* Sub Frame Chirp start indx
481  offset >= 512 */
482 #define RL_RET_CODE_AFRAME_BURST_SIND_1INVAL_IN (96U) /* Sub Frame Chirp start indx >= 512
483  or (Sub Frame Chirp start indx +
484  Sub Frame No. unique Chirps per
485  burst - 1) >= 512*/
486 #define RL_RET_CODE_AFRAME_NUM_BURSTS_INVAL_IN (97U) /* Sub Frame No. bursts is
487  outside[1,512] */
488 #define RL_RET_CODE_AFRAME_BURST_LOOPS_INVAL_IN (98U) /* Sub Frame No. outer loops is
489  outside[1,64] */
490 #define RL_RET_CODE_AFRAME_SF_PERIOD_INVAL_IN (99U) /* Sub Frame period is
491  outside[100us,1.342s] */
492 #define RL_RET_CODE_AFRAME_SF_PERIOD_1INVAL_IN (100U) /* Sub Frame ontime > Sub Frame period
493  or when test source enabled, Sub
494  Frame idale time < 150us */
495 #define RL_RET_CODE_RESERVED9 (101U)
496 #define RL_RET_CODE_AFRAME_TRIG_SEL_INVAL_IN (102U) /* Trigger select is outside[1,2] */
497 #define RL_RET_CODE_AFRAME_TRIG_DELAY_INVAL_IN (103U) /* Frame trigger delay is > 100us */
498 #define RL_RET_CODE_AFRAME_IS_ONGOING (104U) /* API issued when frame is ongoing */
499 
501 #define RL_RET_CODE_TS_POS_VECY_INVAL_IN (105U) /* position vector x[y] < 0 */
502 #define RL_RET_CODE_RESERVED10 (106U)
503 #define RL_RET_CODE_TS_VEL_VECXYZ_INVAL_IN (107U) /* position vector x[x] < 5000 or
504  position vector x[y] < 5000 or
505  position vector x[x] < 5000 */
506 #define RL_RET_CODE_TS_SIG_LEVEL_INVAL_IN (108U) /* SIG_LEV_VECx > 950 */
507 #define RL_RET_CODE_TS_RX_ANT_POS_INVAL_IN (109U) /* RX_ANT_POS_XZ[Bytex] > 120 */
508 #define RL_RET_CODE_RESERVED11 (110U)
509 
511 #define RL_RET_CODE_PROG_FILT_STARTINDX_INVALID (111U) /* Prog. Filter coefficient start
512  indx is odd number */
513 #define RL_RET_CODE_PROG_FILT_PROFILE_INVALID (112U) /* Pro indx >= 4 */
514 #define RL_RET_CODE_PROG_FILT_UNSUPPORTED_DEV (113U) /* API issued for non AWR1642 device*/
515 
517 #define RL_RET_CODE_PERCHIRPPHSHIFT_UNSUPPORTED_DEV (114U) /* API issued for non AWR1243 device*/
518 #define RL_RET_CODE_PERCHIRPPHSHIFT_STIND (115U) /* Chirp Start indx >= 512 */
519 #define RL_RET_CODE_PERCHIRPPHSHIFT_ENIND (116U) /* Chirp End indx >= 512 */
520 #define RL_RET_CODE_PERCHIRPPHSHIFT_WRONG_STIND (117U) /* Chirp Start indx > End indx */
521 
523 #define RL_RET_CODE_RF_INIT_NOT_DONE (118U) /* Boot time calibrations are not
524  done so cannot run runtime calibrations */
525 #define RL_RET_CODE_FREQ_LIMIT_OUT_RANGE (119U) /* Freq. is outside[76GHz,81GHz] or
526  Freq. low limit > high limit */
527 #define RL_RET_CODE_CAL_MON_TIME_INVALID (120U) /* CALIB_MON_TIME_UNIT <= 0 */
528 #define RL_RET_CODE_RUN_CAL_PERIOD_INVALID (121U) /* CALIBRATION_ PERIODICITY = 0 */
529 #define RL_RET_CODE_CONT_STREAM_MODE_EN (122U) /* API is issued when continuous
530  streaming mode is on */
531 #define RL_RET_CODE_RX_GAIN_BOOT_CAL_NOT_DONE (123U) /* RX gain run time calibration was
532  requested but boot time calibration
533  was not performed */
534 #define RL_RET_CODE_LO_DIST_BOOT_CAL_NOT_DONE (124U) /* LO distribution run time
535  calibration was requested but boot time
536  calibration was not performed */
537 #define RL_RET_CODE_TX_PWR_BOOT_CAL_NOT_DONE (125U) /* TX power run time calibration was
538  requested but boot time calibration
539  was not performed */
540 #define RL_RET_CODE_PROG_FILTR_UNSUPPORTED_DFEMODE (126U) /* DFE mode is pseudo real */
541 #define RL_RET_CODE_ADC_BITS_FULL_SCALE_REDUC_INVAL (127U) /* FULL_SCALE_REDUCTION_FACTOR is > 0
542  for 16 bit ADC, or > 2 for 14 bit
543  ADC mode or > 4 for 12 bit ADC mode */
544 
545 #define RL_RET_CODE_CH_CFG_DEV_VRNT_CASC_INVAL_IN (130U) /* Device variant does not allow
546  cascading but API is issued to
547  enable cascading mode */
548 
550 #define RL_RET_CODE_INVAL_LOOPBACK_TYPE (132U)
551 #define RL_RET_CODE_INVAL_LOOPBACK_BURST_IND (133U)
552 #define RL_RET_CODE_INVAL_LOOPBACK_CONFIG (134U)
553 #define RL_RET_CODE_DYN_CHIRP_INVAL_SEG (135U)
554 #define RL_RET_CODE_DYN_PERCHIRP_PHSHFT_INVA_SEG (136U)
555 #define RL_RET_CODE_INVALID_CAL_CHUNK_ID (137U)
556 #define RL_RET_CODE_INVALID_CAL_CHUNK_DATA (138U)
557 
559 #define RL_RET_CODE_RX02_RF_TURN_OFF_TIME_INVALID (139U) /* RX02_RF_TURN_OFF_TIME is not
560  within the range [-1024, 1023] */
561 #define RL_RET_CODE_RX13_RF_TURN_OFF_TIME_INVALID (140U) /* RX13_RF_TURN_OFF_TIME is not
562  within the range [-1024, 1023] */
563 #define RL_RET_CODE_RX02_BB_TURN_OFF_TIME_INVALID (141U) /* RX02_BB_TURN_OFF_TIME is not
564  within the range [-1024, 1023] */
565 #define RL_RET_CODE_RX13_BB_TURN_OFF_TIME_INVALID (142U) /* RX13_BB_TURN_OFF_TIME is not
566  within the range [-1024, 1023] */
567 #define RL_RET_CODE_RX02_RF_PREENABLE_TIME_INVALID (143U) /* RX02_RF_PREENABLE_TIME is not
568  within the range [-1024, 1023] */
569 #define RL_RET_CODE_RX13_RF_PREENABLE_TIME_INVALID (144U) /* RX13_RF_PREENABLE_TIME is not
570  within the range [-1024, 1023] */
571 #define RL_RET_CODE_RX02_BB_PREENABLE_TIME_INVALID (145U) /* RX02_BB_PREENABLE_TIME is not
572  within the range [-1024, 1023] */
573 #define RL_RET_CODE_RX13_BB_PREENABLE_TIME_INVALID (146U) /* RX13_BB_PREENABLE_TIME is not
574  within the range [-1024, 1023] */
575 #define RL_RET_CODE_RX02_RF_TURN_ON_TIME_INVALID (147U) /* RX02_RF_TURN_ON_TIME is not
576  within the range [-1024, 1023] */
577 #define RL_RET_CODE_RX13_RF_TURN_ON_TIME_INVALID (148U) /* RX13_RF_TURN_ON_TIME is not
578  within the range [-1024, 1023] */
579 #define RL_RET_CODE_RX02_BB_TURN_ON_TIME_INVALID (149U) /* RX02_BB_TURN_ON_TIME is not
580  within the range [-1024, 1023] */
581 #define RL_RET_CODE_RX13_BB_TURN_ON_TIME_INVALID (150U) /* RX13_BB_TURN_ON_TIME is not
582  within the range [-1024, 1023] */
583 #define RL_RET_CODE_RX_LO_TURN_OFF_TIME_INVALID (151U) /* RX_LO_TURN_OFF_TIME is not
584  within the range [-1024, 1023] */
585 #define RL_RET_CODE_TX_LO_TURN_OFF_TIME_INVALID (152U) /* TX_LO_TURN_OFF_TIME is not
586  within the range [-1024, 1023] */
587 #define RL_RET_CODE_RX_LO_TURN_ON_TIME_INVALID (153U) /* RX_LO_TURN_ON_TIME is not
588  within the range [-1024, 1023] */
589 #define RL_RET_CODE_TX_LO_TURN_ON_TIME_INVALID (154U) /* TX_LO_TURN_ON_TIME is not
590  within the range [-1024, 1023] */
591 #define RL_RET_CODE_SUBFRAME_TRIGGER_INVALID (155U) /* Sub frame trigger option is not
592  enabled but sub frame trigger API
593  is issued or frame is configured
594  for software trigger mode and
595  sub-frame trigger API is issued */
596 #define RL_RET_CODE_REGULAR_ADC_MODE_INVALID (156U) /* Regular ADC mode is issued on a
597  5 MHz part variant */
598 #define RL_RET_CODE_CHIRP_ROW_SELECT_INVAL_IN (159U) /* Chirp row select is not with in
599  the range [0x00, 0x30] */
600 
601 #define RL_RET_CODE_DEVICE_NOT_ASILB_TYPE (250U) /* Device type is not ASILB */
602 #define RL_RET_CODE_FRAME_ONGOING (251U) /* Fault injection API or Digital
603  latent fault API is issued when
604  frames are ongoing */
605 #define RL_RET_CODE_INVLD_REPO_MODE (252U) /* Invalid reporting mode */
606 #define RL_RET_CODE_INVLD_PROFILE_ID (253U) /* Configured profile ID is not
607  within [0,3] */
608 #define RL_RET_CODE_INVLD_PROFILE (254U) /* Monitoring profile ID is not
609  configured yet */
610 #define RL_RET_CODE_INVLD_EXTSIG_SETLTIME (255U) /* Settling time is configured is
611  more than 12us */
612 #define RL_RET_CODE_INVLD_NO_RX_ENABLED (256U) /* None of the RXs are enabled */
613 #define RL_RET_CODE_INVLD_TX0_NOT_ENABLED (257U) /* TX0 is not enabled */
614 #define RL_RET_CODE_INVLD_TX1_NOT_ENABLED (258U) /* TX1 is not enabled */
615 #define RL_RET_CODE_INVLD_TX2_NOT_ENABLED (259U) /* TX2 is not enabled */
616 #define RL_RET_CODE_MON_INVALID_RF_BIT_MASK (260U) /* Invalid RF bit mask */
617 #define RL_RET_CODE_RESERVED12 (261U)
618 #define RL_RET_CODE_RESERVED13 (262U)
619 #define RL_RET_CODE_MON_TX_EN_CHK_FAIL (263U) /* Monitored TX is not enabled */
620 #define RL_RET_CODE_MON_RX_CH_EN_CHK_FAIL (264U) /* Monitored RX is not enabled */
621 #define RL_RET_CODE_MON_TX_CH_PS_LB (265U) /* TX selected for RX gain phase
622  monitor is TX2 (Only TX0 or TX1 is
623  allowed) */
624 #define RL_RET_CODE_INVLD_SAT_MON_SEL (266U) /* SAT_MON_SEL is not in [0, 3] */
625 #define RL_RET_CODE_INVLD_SAT_MON_PRI_SLICE_DUR (267U) /* SAT_MON_PRIMARY_TIME_SLICE_DURATION
626  is less than 0.64us or greater
627  than ADC sampling time */
628 #define RL_RET_CODE_INVLD_SAT_MON_NUM_SLICES (268U) /* SAT_MON_NUM_SLICES is 0 or
629  greater than 127 */
630 #define RL_RET_CODE_INVLD_SIG_IMG_SLICENUM (269U) /* SIG_IMG_MON_NUM_SLICES is 0 or
631  greater than 127 */
632 #define RL_RET_CODE_INVLD_SIG_IMG_NUMSAMPPERSLICE (270U) /* NUM_SAMPLES_ PER_PRIMARY_TIME_SLICE
633  is odd, or less than 4 in Complex1x
634  mode or less than 8 in non-Complex1x
635  modes or greater than NUM_ADC_SAMPLES*/
636 #define RL_RET_CODE_INVLD_SYNTH_L1_LIN (271U)
637 #define RL_RET_CODE_INVLD_SYNTH_L2_LIN (272U)
638 #define RL_RET_CODE_INVLD_SYNTH_N_LIN (273U)
639 #define RL_RET_CODE_INVLD_SYNTH_MON_START_TIME (274U)
640 #define RL_RET_CODE_INVLD_SYNTH_MON_LIN_RAM_ADDR (275U)
641 #define RL_RET_CODE_LDO_BYPASSED (279U) /* LDO fault inject is requested but
642  LDOs are bypassed */
643 #define RL_RET_CODE_INVLD_SIG_IMG_BAND_MONTR (280U) /* Signal and image band monitor is
644  not supported */
645 #define RL_RET_CODE_ANALOG_MONITOR_NOT_SUPPORTED (281U)
646 #define RL_RET_CODE_ISSUE_TO_ENABLE_CASCASE_MODE (282U) /* Device variant does not allow
647  cascading but API is issued to
648  enable cascading mode */
649 #define RL_RET_CODE_RX_SAT_MON_NOT_SUPPORTED (283U)
650 
651 #define RL_RET_CODE_CHIRP_FAIL (290U) /* Monitoring chirp error */
652 #define RL_RET_CODE_PD_PWR_LVL (291U) /* Loopback power measured by PD
653  is below -40 dBm */
654 #define RL_RET_CODE_ADC_PWR_LVL (292U) /* ADC power is higher than 7 dBm */
655 #define RL_RET_CODE_NOISE_FIG_LOW (293U) /* Noise figure is less than 0 */
656 #define RL_RET_CODE_PD_CDS_ON_FAIL (294U) /* PD measurement with RF on is less
657  than with RF off */
658 #define RL_RET_CODE_PGA_GAIN_FAIL (295U) /* Incorrect PGA gain for monitoring*/
659 
660 /* ADC Config API */
661 #define RL_RET_CODE_RX_CHAN_EN_OOR (1001U) /* numADCBits out of Range */
662 #define RL_RET_CODE_NUM_ADC_BITS_OOR (1002U) /* rxChannelEn out of Range */
663 #define RL_RET_CODE_ADC_OUT_FMT_OOR (1003U) /* adcOutFormat out of Range */
664 #define RL_RET_CODE_IQ_SWAP_SEL_OOR (1004U) /* sampleInterleave out of
665  Range */
666 #define RL_RET_CODE_CHAN_INTERLEAVE_OOR (1005U) /* channelInterleave out of
667  Range */
668 
669 /* Data Path Config API */
670 #define RL_RET_CODE_DATA_INTF_SEL_OOR (1006U) /* dataIntfSel out of Range */
671 #define RL_RET_CODE_DATA_FMT_PKT0_INVALID (1007U) /* dataTransPkt0Format
672  Unsupporetd */
673 #define RL_RET_CODE_DATA_FMT_PKT1_INVALID (1008U) /* dataTransPkt1Format
674  Unsupporetd */
675 
676 /* Lane Enable config API */
677 #define RL_RET_CODE_LANE_ENABLE_OOR (1009U) /* laneEnable is out of range */
678 #define RL_RET_CODE_LANE_ENABLE_INVALID (1010U) /* laneEnable is not supported */
679 
680 /* Lane Clock config API */
681 #define RL_RET_CODE_LANE_CLK_CFG_OOR (1011U) /* laneClkCfg is out of range */
682 #define RL_RET_CODE_LANE_CLK_CFG_INVALID (1012U) /* laneClkCfg is not supported */
683 #define RL_RET_CODE_DATA_RATE_OOR (1013U) /* dataRate is out of range */
684 
685 /* LVDS config API */
686 #define RL_RET_CODE_LANE_FMT_MAP_OOR (1014U) /* laneFmtMap is out of range */
687 #define RL_RET_CODE_LANE_PARAM_CFG_OOR (1015U) /* laneParamCfg is out of range */
688 
689 /* Continuous Streaming Mode API */
690 #define RL_RET_CODE_CONT_STREAM_MODE_OOR (1016U) /* contStreamMode is out of
691  range */
692 #define RL_RET_CODE_CONT_STREAM_MODE_INVALID (1017U) /* contStreamMode is already
693  in requested mode */
694 
695 /* CSI2 Lane Config API */
696 #define RL_RET_CODE_LANE0_POS_POL_OOR (1018U) /* lane0 pos is out of range */
697 #define RL_RET_CODE_LANE1_POS_POL_OOR (1019U) /* lane1 pos is out of range */
698 #define RL_RET_CODE_LANE2_POS_POL_OOR (1020U) /* lane2 pos is out of range */
699 #define RL_RET_CODE_LANE3_POS_POL_OOR (1021U) /* lane3 pos is out of range */
700 #define RL_RET_CODE_CLOCK_POS_OOR (1022U) /* ClockPos is out of range */
701 
702 /* Frame Config Apply API */
703 #define RL_RET_CODE_HALF_WORDS_PER_CHIRP_OOR (1023U) /* adcOutSize is out of range */
704 
705 /* Advanced Frame Config API */
706 #define RL_RET_CODE_NUM_SUBFRAMES_OOR (1024U) /* numSubFrames is out of range */
707 
708 #define RL_RET_CODE_SF1_TOT_NUM_CHIRPS_OOR (1025U) /* totNumChirps is out of range */
709 #define RL_RET_CODE_SF1_NUM_ADC_SAMP_OOR (1026U) /* numADCSamplesInPkt is out
710  of range */
711 #define RL_RET_CODE_SF1_NUM_CHIRPS_OOR (1027U) /* numChirpsInPkt is out of
712  range */
713 
714 #define RL_RET_CODE_SF2_TOT_NUM_CHIRPS_OOR (1028U) /* totNumChirps is out of
715  range */
716 #define RL_RET_CODE_SF2_NUM_ADC_SAMP_OOR (1029U) /* numADCSamplesInPkt is out
717  of range */
718 #define RL_RET_CODE_SF2_NUM_CHIRPS_OOR (1030U) /* numChirpsInPkt is out of
719  range */
720 
721 #define RL_RET_CODE_SF3_TOT_NUM_CHIRPS_OOR (1031U) /* totNumChirps is out of
722  range */
723 #define RL_RET_CODE_SF3_NUM_ADC_SAMP_OOR (1032U) /* numADCSamplesInPkt is out of
724  range */
725 #define RL_RET_CODE_SF3_NUM_CHIRPS_OOR (1033U) /* numChirpsInPkt is out of
726  range */
727 
728 #define RL_RET_CODE_SF4_TOT_NUM_CHIRPS_OOR (1034U) /* totNumChirps is out of
729  range */
730 #define RL_RET_CODE_SF4_NUM_ADC_SAMP_OOR (1035U) /* numADCSamplesInPkt is out of
731  range */
732 #define RL_RET_CODE_SF4_NUM_CHIRPS_OOR (1036U) /* numChirpsInPkt is out of range */
733 
734 #define RL_RET_CODE_MCUCLOCK_CTRL_OOR (1040U) /* mcuClkOutEn is out of range */
735 #define RL_RET_CODE_MCUCLOCK_SRC_OOR (1041U) /* mcuClkOutSrc is out of range */
736 
737 #define RL_RET_CODE_PMICCLOCK_CTRL_OOR (1042U) /* pmicClkOutEn is out of range */
738 #define RL_RET_CODE_PMICCLOCK_SRC_OOR (1043U) /* pmicClkOutSrc is out of range */
739 #define RL_RET_CODE_PMICMODE_SELECT_OOR (1044U) /* modeSel is out of range */
740 #define RL_RET_CODE_PMICFREQ_SLOPE_OOR (1045U) /* freqSlope is out of range */
741 #define RL_RET_CODE_PMICCLK_DITHER_EN_OOR (1046U) /* clkDitherEn is out of range */
742 
743 #define RL_RET_CODE_TESTPATTERN_EN_OOR (1047U) /* testPatternGenEn is out of
744  range */
745 #define RL_RET_CODE_LFAULTTEST_UNSUPPORTED_OOR (1048U)
746 
747 
753 #define RL_DISABLE_LOGGING 1
754 
755 /* mmwavelink MACROs for Error Checks */
756 #define RL_OSI_RET_CODE_OK (0)
757 #define RL_IF_RET_CODE_OK (0)
758 
759 #ifdef RL_EXTENDED_MESSAGE /* build time MACRO to change message size */
760 /* if mmWaveLink instance is running inside xWR1443/1642 device then Max size of packet can
761  be (2048 -4) bytes, where 4 bytes are reserved for mailbox header */
762 #define RL_MAX_SIZE_MSG (2044U)
763 #else
764 #define RL_MAX_SIZE_MSG (256U)
765 #endif
766 
767 
778 #define RL_DEVICE_MAP_NATIVE (0U)
779 #define RL_DEVICE_MAP_CASCADED_1 (1U)
780 #define RL_DEVICE_MAP_CASCADED_2 (2U)
781 #define RL_DEVICE_MAP_CASCADED_3 (4U)
782 #define RL_DEVICE_MAP_CASCADED_4 (8U)
784 /* AWR1243 Device Map - Max Cascading */
785 #define RL_DEVICE_MAP_CASCADED_ALL (RL_DEVICE_MAP_CASCADED_1 |\
786  RL_DEVICE_MAP_CASCADED_2 |\
787  RL_DEVICE_MAP_CASCADED_3 |\
788  RL_DEVICE_MAP_CASCADED_4)
789 
790 /* Device Index for SubSystem */
791 #define RL_DEVICE_INDEX_INTERNAL_BSS (0U)
792 #define RL_DEVICE_INDEX_INTERNAL_DSS_MSS (1U)
793 #define RL_DEVICE_INDEX_INTERNAL_HOST (2U)
796 #define RL_DEVICE_MAP_INTERNAL_BSS (RL_DEVICE_MAP_CASCADED_1)
798 #define RL_DEVICE_MAP_INTERNAL_DSS_MSS (RL_DEVICE_MAP_CASCADED_2)
799 #define RL_DEVICE_MAP_INTERNAL_HOST (RL_DEVICE_MAP_CASCADED_3)
802 #define RL_DEVICE_CONNECTED_MAX (4U)
803 
807 #define RL_CRC_TYPE_16BIT_CCITT (0U)
808 #define RL_CRC_TYPE_32BIT (1U)
809 #define RL_CRC_TYPE_64BIT_ISO (2U)
810 #define RL_CRC_TYPE_NO_CRC (3U)
815 #define RL_PLATFORM_HOST (0x0U)
816 #define RL_PLATFORM_MSS (0x1U)
817 #define RL_PLATFORM_DSS (0x2U)
822 #define RL_AR_DEVICETYPE_12XX (0x0U)
823 #define RL_AR_DEVICETYPE_14XX (0x1U)
824 #define RL_AR_DEVICETYPE_16XX (0x2U)
825 #define RL_AR_DEVICETYPE_18XX (0x3U)
826 #define RL_AR_DEVICETYPE_68XX (0x4U)
831 #define RL_DBG_LEVEL_NONE ((rlUInt8_t)0U)
832 #define RL_DBG_LEVEL_ERROR ((rlUInt8_t)1U)
833 #define RL_DBG_LEVEL_WARNING ((rlUInt8_t)2U)
834 #define RL_DBG_LEVEL_INFO ((rlUInt8_t)3U)
835 #define RL_DBG_LEVEL_DEBUG ((rlUInt8_t)4U)
836 #define RL_DBG_LEVEL_VERBOSE ((rlUInt8_t)5U)
837 
841 #define RL_SENSOR_ANTENA_ONE (0U)
842 #define RL_SENSOR_ANTENA_TWO (1U)
843 #define RL_SENSOR_ANTENA_THREE (2U)
844 #define RL_SENSOR_ANTENA_FOUR (3U)
845 #define RL_SENSOR_IFORCE (4U)
846 #define RL_SENSOR_VSENSE (5U)
847 #define RL_SENSOR_IFORCEBUF (6U)
848 #define RL_SENSOR_RESERVED0 (7U)
849 #define RL_SENSOR_RESERVED1 (8U)
850 #define RL_SENSOR_RESERVED2 (9U)
851 #define RL_SENSOR_RESERVED3 (10U)
852 #define RL_SENSOR_RESERVED4 (11U)
853 #define RL_MAX_GPADC_SENSORS (12U)
854 
858 #define RL_SWAP_32(x) (((x) & 0x0000FFFFU)<<16U)|(((x) & 0xFFFF0000U)>>16U);
859 
860 /******************************************************************************
861  * TYPE-DEFINE STRUCT/ENUM/UNION DEFINITIONS
862  ******************************************************************************
863  */
864 
865 /* DesignId : MMWL_DesignId_001 */
866 /* Requirements : AUTORADAR_REQ-697, AUTORADAR_REQ-698, AUTORADAR_REQ-699, AUTORADAR_REQ-700,
867  AUTORADAR_REQ-701, AUTORADAR_REQ-702, AUTORADAR_REQ-703, AUTORADAR_REQ-704,
868  AUTORADAR_REQ-705, AUTORADAR_REQ-706, AUTORADAR_REQ-830, AUTORADAR_REQ-831,
869  AUTORADAR_REQ-832, AUTORADAR_REQ-888, AUTORADAR_REQ-889, AUTORADAR_REQ-890
870 */
871 
875 typedef rlInt32_t rlReturnVal_t;
876 
880 typedef rlUInt8_t rlCrcType_t;
881 
882 /* Function pointers for spawn task function and event handlers*/
883 
887 typedef void (*RL_P_OSI_SPAWN_ENTRY)(const void* pValue);
888 
892 typedef void (*RL_P_EVENT_HANDLER)(rlUInt8_t deviceIndex, void* pValue);
893 
897 typedef struct rlComIfCbs
898 {
909  /* DesignId : MMWL_DesignId_004 */
910  /* Requirements : AUTORADAR_REQ-785 */
911  rlComIfHdl_t (*rlComIfOpen)(rlUInt8_t deviceIndex, rlUInt32_t flags);
912 
924  /* DesignId : MMWL_DesignId_004 */
925  /* Requirements : AUTORADAR_REQ-785 */
926  rlInt32_t (*rlComIfRead)(rlComIfHdl_t fd, rlUInt8_t *pBuff, rlUInt16_t len);
927 
939  /* DesignId : */
940  /* Requirements : AUTORADAR_REQ-785 */
941  rlInt32_t (*rlComIfWrite)(rlComIfHdl_t fd, rlUInt8_t *pBuff, rlUInt16_t len);
942 
952  /* DesignId : MMWL_DesignId_004 */
953  /* Requirements : AUTORADAR_REQ-785 */
954  rlInt32_t (*rlComIfClose)(rlComIfHdl_t fd);
955 }rlComIfCbs_t;
956 
960 typedef struct rlOsiMutexCbs
961 {
972  /* DesignId : MMWL_DesignId_004 */
973  /* Requirements : AUTORADAR_REQ-784 */
974  rlInt32_t (*rlOsiMutexCreate)(rlOsiMutexHdl_t* mutexHdl, rlInt8_t* name);
975 
986  /* DesignId : MMWL_DesignId_004 */
987  /* Requirements : AUTORADAR_REQ-784 */
988  rlInt32_t (*rlOsiMutexLock)(rlOsiMutexHdl_t* mutexHdl, rlOsiTime_t timeout);
989 
999  /* DesignId : MMWL_DesignId_004 */
1000  /* Requirements : AUTORADAR_REQ-784 */
1001  rlInt32_t (*rlOsiMutexUnLock)(rlOsiMutexHdl_t* mutexHdl);
1002 
1012  /* DesignId : MMWL_DesignId_004 */
1013  /* Requirements : AUTORADAR_REQ-784 */
1014  rlInt32_t (*rlOsiMutexDelete)(rlOsiMutexHdl_t* mutexHdl);
1015 }rlOsiMutexCbs_t;
1016 
1020 typedef struct rlOsiSemCbs
1021 {
1032  /* DesignId : MMWL_DesignId_004 */
1033  /* Requirements : AUTORADAR_REQ-784 */
1034  rlInt32_t (*rlOsiSemCreate)(rlOsiSemHdl_t* semHdl, rlInt8_t* name);
1035 
1046  /* DesignId : MMWL_DesignId_004 */
1047  /* Requirements : AUTORADAR_REQ-784 */
1048  rlInt32_t (*rlOsiSemWait)(rlOsiSemHdl_t* semHdl, rlOsiTime_t timeout);
1049 
1059  /* DesignId : MMWL_DesignId_004 */
1060  /* Requirements : AUTORADAR_REQ-784 */
1061  rlInt32_t (*rlOsiSemSignal)(rlOsiSemHdl_t* semHdl);
1062 
1072  /* DesignId : MMWL_DesignId_004 */
1073  /* Requirements : AUTORADAR_REQ-784 */
1074  rlInt32_t (*rlOsiSemDelete)(rlOsiSemHdl_t* semHdl);
1075 }rlOsiSemCbs_t;
1076 
1080 typedef struct rlOsiMsgQCbs
1081 {
1095  /* DesignId : MMWL_DesignId_004 */
1096  /* Requirements : AUTORADAR_REQ-784 */
1097  rlInt32_t (*rlOsiSpawn)(RL_P_OSI_SPAWN_ENTRY pEntry, const void* pValue, rlUInt32_t flags);
1098 }rlOsiMsgQCbs_t;
1099 
1100 
1104 typedef struct rlOsiCbs
1105 {
1109  rlOsiMutexCbs_t mutex;
1113  rlOsiSemCbs_t sem;
1117  rlOsiMsgQCbs_t queue;
1118 }rlOsiCbs_t;
1119 
1123 typedef struct rlEventCbs
1124 {
1138  /* DesignId : MMWL_DesignId_004 */
1139  /* Requirements : AUTORADAR_REQ-783 */
1140  void (*rlAsyncEvent)(rlUInt8_t devIndex, rlUInt16_t subId, rlUInt16_t subLen,
1141  rlUInt8_t *payload);
1142 }rlEventCbs_t;
1143 
1147 typedef struct rlTimerCbs
1148 {
1149  rlInt32_t (*rlDelay)(rlUInt32_t delay);
1150 }rlTimerCbs_t;
1151 
1155 typedef struct rlCmdParserCbs
1156 {
1157  rlInt32_t (*rlCmdParser)(rlUInt8_t rxMsgClass, rlInt32_t inVal);
1158  rlInt32_t (*rlPostCnysStep)(rlUInt8_t devIndex);
1159 }rlCmdParserCbs_t;
1160 
1164 typedef struct rlCrcCbs
1165 {
1180  /* DesignId : */
1181  /* Requirements : */
1182  rlInt32_t (*rlComputeCRC)(rlUInt8_t* data, rlUInt32_t dataLen, rlUInt8_t crcType,
1183  rlUInt8_t* crc);
1184 }rlCrcCbs_t;
1185 
1189 typedef struct rlDeviceCtrlCbs
1190 {
1201  /* DesignId : MMWL_DesignId_004 */
1202  /* Requirements : AUTORADAR_REQ-786 */
1203  rlInt32_t (*rlDeviceEnable)(rlUInt8_t deviceIndex);
1204 
1215  /* DesignId : MMWL_DesignId_004 */
1216  /* Requirements : AUTORADAR_REQ-786 */
1217  rlInt32_t (*rlDeviceDisable)(rlUInt8_t deviceIndex);
1218 
1227  /* DesignId : MMWL_DesignId_004 */
1228  /* Requirements : AUTORADAR_REQ-787 */
1229  void (*rlDeviceMaskHostIrq)(rlComIfHdl_t fd);
1230 
1239  /* DesignId : MMWL_DesignId_004 */
1240  /* Requirements : AUTORADAR_REQ-787 */
1241  void (*rlDeviceUnMaskHostIrq)(rlComIfHdl_t fd);
1242 
1257  /* DesignId :MMWL_DesignId_004 */
1258  /* Requirements : AUTORADAR_REQ-787 */
1259  rlInt32_t (*rlDeviceWaitIrqStatus)(rlComIfHdl_t fd, rlUInt8_t highLow);
1260 
1270  /* DesignId : MMWL_DesignId_004 */
1271  /* Requirements : AUTORADAR_REQ-787 */
1272  rlUInt16_t (*rlCommIfAssertIrq)(rlUInt8_t highLow);
1273 
1289  /* DesignId : MMWL_DesignId_026 */
1290  /* Requirements : AUTORADAR_REQ-777 */
1291  rlInt32_t (*rlRegisterInterruptHandler)(rlUInt8_t deviceIndex,
1292  RL_P_EVENT_HANDLER pHandler, void* pValue);
1293 }rlDeviceCtrlCbs_t;
1297 typedef rlInt32_t (*rlPrintFptr)(const rlInt8_t* format, ...);
1298 
1302 typedef struct rlDbgCb
1303 {
1315  /* DesignId : */
1316  /* Requirements : */
1317  rlPrintFptr rlPrint;
1321  rlUInt8_t dbgLevel;
1322 }rlDbgCb_t;
1323 
1327 typedef struct rlClientCbs
1328 {
1332  rlComIfCbs_t comIfCb;
1336  rlOsiCbs_t osiCb;
1340  rlEventCbs_t eventCb;
1344  rlDeviceCtrlCbs_t devCtrlCb;
1348  rlTimerCbs_t timerCb;
1353  rlCmdParserCbs_t cmdParserCb;
1357  rlCrcCbs_t crcCb;
1361  rlCrcType_t crcType;
1367  rlUInt32_t ackTimeout;
1373  rlUInt8_t platform;
1378  rlUInt8_t arDevType;
1382  rlDbgCb_t dbgCb;
1383 }rlClientCbs_t;
1384 
1390 typedef struct rlInitComplete
1391 {
1395  rlUInt32_t powerUpTime;
1432  rlUInt64_t powerUpStatus;
1472  rlUInt64_t bootTestStatus;
1473 }rlInitComplete_t;
1474 
1478 typedef struct rlStartComplete
1479 {
1512  rlUInt32_t status;
1516  rlUInt32_t powerUpTime;
1520  rlUInt32_t reserved0;
1524  rlUInt32_t reserved1;
1525 }rlStartComplete_t;
1526 
1527 
1531 typedef struct rlMssEsmFault
1532 {
1568  rlUInt32_t esmGrp1Err;
1604  rlUInt32_t esmGrp2Err;
1608  rlUInt32_t reserved;
1609 }rlMssEsmFault_t;
1610 
1617 typedef struct rlMssBootErrStatus
1618 {
1622  rlUInt32_t powerUpTime;
1659  rlUInt64_t powerUpStatus;
1699  rlUInt64_t bootTestStatus;
1700 }rlMssBootErrStatus_t;
1701 
1706 typedef struct rlMssLatentFaultReport
1707 {
1744  rlUInt32_t testStatusFlg;
1748  rlUInt32_t reserved;
1749 }rlMssLatentFaultReport_t;
1750 
1751 
1756 typedef struct rlMssPeriodicTestStatus
1757 {
1765  rlUInt32_t testStatusFlg;
1769  rlUInt32_t reserved;
1770 }rlMssPeriodicTestStatus_t;
1771 
1772 
1777 typedef struct rlMssRfErrStatus
1778 {
1788  rlUInt32_t errStatusFlg;
1792  rlUInt32_t reserved;
1793 }rlMssRfErrStatus_t;
1794 
1798 typedef struct rlBssEsmFault
1799 {
1825  rlUInt32_t esmGrp1Err;
1861  rlUInt32_t esmGrp2Err;
1862 }rlBssEsmFault_t;
1863 
1869 typedef struct rlVmonErrStatus
1870 {
1871 #ifndef MMWL_BIG_ENDIAN
1872 
1878  rlUInt8_t faultType;
1882  rlUInt8_t reserved0;
1883 #else
1884 
1887  rlUInt8_t reserved0;
1894  rlUInt8_t faultType;
1895 #endif
1896 
1899  rlUInt16_t reserved1;
1912  rlUInt32_t faultSig;
1916  rlUInt32_t reserved2;
1917 }rlVmonErrStatus_t;
1918 
1925 typedef struct rlRcvAdcData
1926 {
1930  rlUInt16_t remChunks;
1934  rlSInt8_t adcData[220U];
1935 }rlRcvAdcData_t;
1936 
1940 typedef struct rlRfInitComplete
1941 {
1963  rlUInt32_t calibStatus;
1968  rlUInt32_t calibUpdate;
1974  rlUInt16_t temperature;
1978  rlUInt16_t reserved0;
1984  rlUInt32_t timeStamp;
1988  rlUInt32_t reserved1;
1989 }rlRfInitComplete_t;
1990 
1996 typedef struct rlRfRunTimeCalibReport
1997 {
2017  rlUInt32_t calibErrorFlag;
2023  rlUInt32_t calibUpdateStatus;
2029  rlInt16_t temperature;
2033  rlUInt16_t reserved0;
2039  rlUInt32_t timeStamp;
2043  rlUInt32_t reserved1;
2044 }rlRfRunTimeCalibReport_t;
2045 
2049 typedef struct rlRfApllCalDone
2050 {
2051  rlUInt16_t apllClCalStatus;
2055  rlUInt16_t cccTolerance;
2059  rlUInt16_t cccCount0;
2063  rlUInt16_t measFreqCount;
2067  rlUInt32_t cccCount1;
2068 }rlRfApllCalDone_t;
2069 
2073 typedef struct rlRfTempData
2074 {
2078  rlUInt32_t time;
2082  rlInt16_t tmpRx0Sens;
2086  rlInt16_t tmpRx1Sens;
2090  rlInt16_t tmpRx2Sens;
2094  rlInt16_t tmpRx3Sens;
2098  rlInt16_t tmpTx0Sens;
2102  rlInt16_t tmpTx1Sens;
2106  rlInt16_t tmpTx2Sens;
2110  rlInt16_t tmpPmSens;
2114  rlInt16_t tmpDig0Sens;
2120  rlInt16_t tmpDig1Sens;
2121 }rlRfTempData_t;
2122 
2127 typedef struct rlCpuFault
2128 {
2129 #ifndef MMWL_BIG_ENDIAN
2130 
2137  rlUInt8_t faultType;
2141  rlUInt8_t reserved0;
2142 #else
2143 
2146  rlUInt8_t reserved0;
2154  rlUInt8_t faultType;
2155 #endif
2156 
2160  rlUInt16_t lineNum;
2164  rlUInt32_t faultLR;
2169  rlUInt32_t faultPrevLR;
2173  rlUInt32_t faultSpsr;
2177  rlUInt32_t faultSp;
2182  rlUInt32_t faultAddr;
2195  rlUInt16_t faultErrStatus;
2196 #ifndef MMWL_BIG_ENDIAN
2197 
2203  rlUInt8_t faultErrSrc;
2209  rlUInt8_t faultAxiErrType;
2215  rlUInt8_t faultAccType;
2222  rlUInt8_t faultRecovType;
2223 #else
2224 
2229  rlUInt8_t faultAxiErrType;
2236  rlUInt8_t faultErrSrc;
2243  rlUInt8_t faultRecovType;
2249  rlUInt8_t faultAccType;
2250 #endif
2251 
2254  rlUInt16_t reserved1;
2255 }rlCpuFault_t;
2256 
2260 typedef struct rlFwVersionParam
2261 {
2262 #ifndef MMWL_BIG_ENDIAN
2263 
2266  rlUInt8_t hwVarient;
2270  rlUInt8_t hwMajor;
2274  rlUInt8_t hwMinor;
2278  rlUInt8_t fwMajor;
2282  rlUInt8_t fwMinor;
2286  rlUInt8_t fwBuild;
2290  rlUInt8_t fwDebug;
2294  rlUInt8_t fwYear;
2298  rlUInt8_t fwMonth;
2302  rlUInt8_t fwDay;
2306  rlUInt8_t patchMajor;
2310  rlUInt8_t patchMinor;
2314  rlUInt8_t patchYear;
2318  rlUInt8_t patchMonth;
2322  rlUInt8_t patchDay;
2328  rlUInt8_t patchBuildDebug;
2329 #else
2330 
2333  rlUInt8_t hwMajor;
2337  rlUInt8_t hwVarient;
2341  rlUInt8_t fwMajor;
2345  rlUInt8_t hwMinor;
2349  rlUInt8_t fwBuild;
2353  rlUInt8_t fwMinor;
2357  rlUInt8_t fwYear;
2361  rlUInt8_t fwDebug;
2365  rlUInt8_t fwDay;
2369  rlUInt8_t fwMonth;
2373  rlUInt8_t patchMinor;
2377  rlUInt8_t patchMajor;
2381  rlUInt8_t patchMonth;
2385  rlUInt8_t patchYear;
2391  rlUInt8_t patchBuildDebug;
2395  rlUInt8_t patchDay;
2396 #endif
2397 }rlFwVersionParam_t;
2398 
2402 typedef struct rlSwVersionParam
2403 {
2404 #ifndef MMWL_BIG_ENDIAN
2405 
2408  rlUInt8_t major;
2412  rlUInt8_t minor;
2416  rlUInt8_t build;
2420  rlUInt8_t debug;
2424  rlUInt8_t year;
2428  rlUInt8_t month;
2432  rlUInt8_t day;
2436  rlUInt8_t reserved;
2437 #else
2438 
2441  rlUInt8_t minor;
2445  rlUInt8_t major;
2449  rlUInt8_t debug;
2453  rlUInt8_t build;
2457  rlUInt8_t month;
2461  rlUInt8_t year;
2465  rlUInt8_t reserved;
2469  rlUInt8_t day;
2470 #endif
2471 }rlSwVersionParam_t;
2472 
2476 typedef struct rlVersion
2477 {
2481  rlFwVersionParam_t master;
2485  rlFwVersionParam_t rf;
2489  rlSwVersionParam_t mmWaveLink;
2490 }rlVersion_t;
2491 
2495 typedef struct rlGpAdcData
2496 {
2500  rlUInt16_t min;
2504  rlUInt16_t max;
2508  rlUInt16_t avg;
2509 } rlGpAdcData_t;
2510 
2514 typedef struct rlRecvdGpAdcData
2515 {
2519  rlGpAdcData_t sensor[RL_MAX_GPADC_SENSORS];
2520 } rlRecvdGpAdcData_t;
2521 
2525 typedef struct rlAnalogFaultReportData
2526 {
2527 #ifndef MMWL_BIG_ENDIAN
2528 
2535  rlUInt8_t faultType;
2539  rlUInt8_t reserved0;
2540 #else
2541 
2544  rlUInt8_t reserved0;
2552  rlUInt8_t faultType;
2553 #endif
2554 
2557  rlUInt16_t reserved1;
2567  rlUInt32_t faultSig;
2571  rlUInt32_t reserved2;
2572 } rlAnalogFaultReportData_t;
2573 
2578 typedef struct rlCalMonTimingErrorReportData
2579 {
2592  rlUInt16_t timingFailCode;
2593  rlUInt16_t reserved;
2594 }rlCalMonTimingErrorReportData_t;
2595 
2599 typedef struct rlDigLatentFaultReportData
2600 {
2633  rlUInt32_t digMonLatentFault;
2634 }rlDigLatentFaultReportData_t;
2635 
2640 typedef struct rlMonReportHdrData
2641 {
2645  rlUInt32_t fttiCount;
2649  rlUInt16_t avgTemp;
2653  rlUInt16_t reserved0;
2657  rlUInt32_t reserved1;
2658 }rlMonReportHdrData_t;
2659 
2664 typedef struct rlDigPeriodicReportData
2665 {
2675  rlUInt32_t digMonPeriodicStatus;
2681  rlUInt32_t timeStamp;
2682 }rlDigPeriodicReportData_t;
2683 
2690 typedef struct rlMonTempReportData
2691 {
2704  rlUInt16_t statusFlags;
2708  rlUInt16_t errorCode;
2726  rlInt16_t tempValues[10U];
2730  rlUInt32_t reserved;
2736  rlUInt32_t timeStamp;
2737 }rlMonTempReportData_t;
2738 
2745 typedef struct rlMonRxGainPhRep
2746 {
2758  rlUInt16_t statusFlags;
2762  rlUInt16_t errorCode;
2763 #ifndef MMWL_BIG_ENDIAN
2764 
2767  rlUInt8_t profIndex;
2771  rlUInt8_t reserved0;
2772 #else
2773 
2776  rlUInt8_t reserved0;
2780  rlUInt8_t profIndex;
2781 #endif
2782 
2785  rlUInt16_t reserved1;
2800  rlUInt16_t rxGainVal[12U];
2815  rlUInt16_t rxPhaseVal[12U];
2819  rlUInt32_t reserved2;
2823  rlUInt32_t reserved3;
2829  rlUInt32_t timeStamp;
2830 }rlMonRxGainPhRep_t;
2831 
2839 typedef struct rlMonRxNoiseFigRep
2840 {
2849  rlUInt16_t statusFlags;
2853  rlUInt16_t errorCode;
2854 #ifndef MMWL_BIG_ENDIAN
2855 
2858  rlUInt8_t profIndex;
2862  rlUInt8_t reserved0;
2863 #else
2864 
2867  rlUInt8_t reserved0;
2871  rlUInt8_t profIndex;
2872 #endif
2873 
2876  rlUInt16_t reserved1;
2890  rlUInt16_t rxNoiseFigVal[12U];
2894  rlUInt32_t reserved2;
2898  rlUInt32_t reserved3;
2902  rlUInt32_t reserved4;
2908  rlUInt32_t timeStamp;
2909 }rlMonRxNoiseFigRep_t;
2910 
2917 typedef struct rlMonRxIfStageRep
2918 {
2929  rlUInt16_t statusFlags;
2933  rlUInt16_t errorCode;
2934 #ifndef MMWL_BIG_ENDIAN
2935 
2938  rlUInt8_t profIndex;
2942  rlUInt8_t reserved0;
2943 #else
2944 
2947  rlUInt8_t reserved0;
2951  rlUInt8_t profIndex;
2952 #endif
2953 
2956  rlUInt16_t reserved1;
2957 #ifndef MMWL_BIG_ENDIAN
2958 
2974  rlInt8_t hpfCutOffFreqEr[8U];
2992  rlInt8_t lpfCutOffFreqEr[8U];
3006  rlInt8_t rxIfaGainErVal[8U];
3007 
3012  rlInt8_t ifGainExp;
3013 
3017  rlUInt8_t reserved2;
3018 #else
3019 
3036  rlInt8_t hpfCutOffFreqEr[8U];
3054  rlInt8_t lpfCutOffFreqEr[8U];
3068  rlInt8_t rxIfaGainErVal[8U];
3069 
3073  rlUInt8_t reserved2;
3074 
3079  rlInt8_t ifGainExp;
3080 #endif
3081 
3084  rlUInt16_t reserved3;
3088  rlUInt32_t reserved4;
3093  rlUInt32_t timeStamp;
3094 }rlMonRxIfStageRep_t;
3095 
3103 typedef struct rlMonTxPowRep
3104 {
3114  rlUInt16_t statusFlags;
3118  rlUInt16_t errorCode;
3119 #ifndef MMWL_BIG_ENDIAN
3120 
3123  rlUInt8_t profIndex;
3127  rlUInt8_t reserved0;
3128 #else
3129 
3132  rlUInt8_t reserved0;
3136  rlUInt8_t profIndex;
3137 #endif
3138 
3141  rlUInt16_t reserved1;
3153  rlInt16_t txPowVal[3U];
3157  rlUInt16_t reserved2;
3163  rlUInt32_t timeStamp;
3164 }rlMonTxPowRep_t;
3165 
3174 typedef struct rlMonTxBallBreakRep
3175 {
3184  rlUInt16_t statusFlags;
3188  rlUInt16_t errorCode;
3193  rlInt16_t txReflCoefVal;
3197  rlUInt16_t reserved0;
3201  rlUInt32_t reserved1;
3207  rlUInt32_t timeStamp;
3208 }rlMonTxBallBreakRep_t;
3209 
3216 typedef struct rlMonTxGainPhaMisRep
3217 {
3227  rlUInt16_t statusFlags;
3231  rlUInt16_t errorCode;
3232 #ifndef MMWL_BIG_ENDIAN
3233 
3236  rlUInt8_t profIndex;
3240  rlUInt8_t reserved0;
3241 #else
3242 
3245  rlUInt8_t reserved0;
3249  rlUInt8_t profIndex;
3250 #endif
3251 
3254  rlUInt16_t reserved1;
3267  rlInt16_t txGainVal[9U];
3281  rlUInt16_t txPhaVal[9U];
3285  rlUInt32_t reserved2;
3289  rlUInt32_t reserved3;
3294  rlUInt32_t timeStamp;
3295 }rlMonTxGainPhaMisRep_t;
3296 
3304 typedef struct rlMonTxBpmRep
3305 {
3315  rlUInt16_t statusFlags;
3319  rlUInt16_t errorCode;
3320 #ifndef MMWL_BIG_ENDIAN
3321 
3324  rlUInt8_t profIndex;
3331  rlUInt8_t phaseShifterMonVal2Msb;
3332 #else
3333 
3339  rlUInt8_t phaseShifterMonVal2Msb;
3343  rlUInt8_t profIndex;
3344 #endif
3345 
3349  rlUInt16_t phaseShifterMonVal1;
3355  rlUInt16_t txBpmPhaDiff;
3356 #ifndef MMWL_BIG_ENDIAN
3357 
3363  rlInt8_t txBpmAmpDiff;
3370  rlUInt8_t phaseShifterMonVal2Lsb;
3371 #else
3372 
3378  rlUInt8_t phaseShifterMonVal2Lsb;
3385  rlInt8_t txBpmAmpDiff;
3386 #endif
3387 
3392  rlUInt32_t timeStamp;
3393 }rlMonTxBpmRep_t;
3394 
3401 typedef struct rlMonSynthFreqRep
3402 {
3411  rlUInt16_t statusFlags;
3415  rlUInt16_t errorCode;
3416 #ifndef MMWL_BIG_ENDIAN
3417 
3420  rlUInt8_t profIndex;
3424  rlUInt8_t reserved0;
3425 #else
3426 
3429  rlUInt8_t reserved0;
3433  rlUInt8_t profIndex;
3434 #endif
3435 
3438  rlUInt16_t reserved1;
3446  rlInt32_t maxFreqErVal;
3455  rlUInt32_t freqFailCnt;
3459  rlUInt32_t reserved2;
3463  rlUInt32_t reserved3;
3469  rlUInt32_t timeStamp;
3470 }rlMonSynthFreqRep_t;
3471 
3478 typedef struct rlMonExtAnaSigRep
3479 {
3493  rlUInt16_t statusFlags;
3497  rlUInt16_t errorCode;
3509  rlInt16_t extAnaSigVal[6U];
3513  rlUInt32_t reserved;
3519  rlUInt32_t timeStamp;
3520 }rlMonExtAnaSigRep_t;
3521 
3528 typedef struct rlMonTxIntAnaSigRep
3529 {
3539  rlUInt16_t statusFlags;
3543  rlUInt16_t errorCode;
3544 #ifndef MMWL_BIG_ENDIAN
3545 
3548  rlUInt8_t profIndex;
3552  rlUInt8_t reserved0;
3553 #else
3554 
3557  rlUInt8_t reserved0;
3561  rlUInt8_t profIndex;
3562 #endif
3563 
3566  rlUInt16_t reserved1;
3572  rlUInt32_t timeStamp;
3573 }rlMonTxIntAnaSigRep_t;
3574 
3581 typedef struct rlMonRxIntAnaSigRep
3582 {
3602  rlUInt16_t statusFlags;
3606  rlUInt16_t errorCode;
3607 #ifndef MMWL_BIG_ENDIAN
3608 
3611  rlUInt8_t profIndex;
3615  rlUInt8_t reserved0;
3616 #else
3617 
3620  rlUInt8_t reserved0;
3624  rlUInt8_t profIndex;
3625 #endif
3626 
3629  rlUInt16_t reserved1;
3635  rlUInt32_t timeStamp;
3636 }rlMonRxIntAnaSigRep_t;
3637 
3644 typedef struct rlMonPmclkloIntAnaSigRep
3645 {
3657  rlUInt16_t statusFlags;
3661  rlUInt16_t errorCode;
3662 #ifndef MMWL_BIG_ENDIAN
3663 
3666  rlUInt8_t profIndex;
3671  rlInt8_t sync20GPower;
3672 #else
3673 
3677  rlInt8_t sync20GPower;
3681  rlUInt8_t profIndex;
3682 #endif
3683 
3686  rlUInt16_t reserved;
3692  rlUInt32_t timeStamp;
3693 }rlMonPmclkloIntAnaSigRep_t;
3694 
3701 typedef struct rlMonGpadcIntAnaSigRep
3702 {
3712  rlUInt16_t statusFlags;
3716  rlUInt16_t errorCode;
3722  rlInt16_t gpadcRef1Val;
3728  rlUInt16_t gpadcRef2Val;
3732  rlUInt32_t reserved;
3738  rlUInt32_t timeStamp;
3739 }rlMonGpadcIntAnaSigRep_t;
3740 
3747 typedef struct rlMonPllConVoltRep
3748 {
3763  rlUInt16_t statusFlags;
3767  rlUInt16_t errorCode;
3787  rlInt16_t pllContVoltVal[8U];
3791  rlUInt32_t reserved;
3797  rlUInt32_t timeStamp;
3798 }rlMonPllConVoltRep_t;
3799 
3806 typedef struct rlMonDccClkFreqRep
3807 {
3821  rlUInt16_t statusFlags;
3825  rlUInt16_t errorCode;
3840  rlUInt16_t freqMeasVal[8U];
3844  rlUInt32_t reserved;
3850  rlUInt32_t timeStamp;
3851 }rlMonDccClkFreqRep_t;
3852 
3853 
3860 typedef struct rlMonRxMixrInPwrRep
3861 {
3873  rlUInt16_t statusFlags;
3877  rlUInt16_t errorCode;
3878 
3879 #ifndef MMWL_BIG_ENDIAN
3880 
3883  rlUInt8_t profIndex;
3887  rlUInt8_t reserved0;
3888 #else
3889 
3892  rlUInt8_t reserved0;
3896  rlUInt8_t profIndex;
3897 #endif
3898 
3901  rlUInt16_t reserved1;
3914  rlUInt32_t rxMixInVolt;
3918  rlUInt32_t reserved2;
3923  rlUInt32_t timeStamp;
3924 }rlMonRxMixrInPwrRep_t;
3925 
3926 
3927 #include <ti/control/mmwavelink/include/rl_device.h>
3928 #include <ti/control/mmwavelink/include/rl_sensor.h>
3929 #include <ti/control/mmwavelink/include/rl_monitoring.h>
3930 #include <ti/control/mmwavelink/include/rl_protocol.h>
3931 #include <ti/control/mmwavelink/include/rl_messages.h>
3932 
3933 
3934 /******************************************************************************
3935  * FUNCTION PROTOTYPES
3936  ******************************************************************************
3937  */
3938 
3939 #ifdef __cplusplus
3940 }
3941 #endif
3942 
3943 #endif
3944 /*
3945  * END OF MMWAVELINK_H
3946  */
3947 
rlMonDccClkFreqRep_t
This is the Monitoring report which RadarSS sends to the host, containing information about the relat...
Definition: mmwavelink.h:3809
rlRfRunTimeCalibReport_t
mmWaveLink RF Run time calibration report for event RL_RF_AE_RUN_TIME_CALIB_REPORT_SB ...
Definition: mmwavelink.h:1999
rlDigPeriodicReportData_t
This async event is sent periodically to indicate the status of periodic digital monitoring tests...
Definition: mmwavelink.h:2667
rlClientCbs_t
mmWaveLink client callback structure
Definition: mmwavelink.h:1330
rlMonRxNoiseFigRep_t
This is the Monitoring report which RadarSS sends to the host, containing the measured RX noise figur...
Definition: mmwavelink.h:2842
rlRfInitComplete_t
mmWaveLink RF Init Complete data structure for event RL_RF_AE_INITCALIBSTATUS_SB
Definition: mmwavelink.h:1943
rlRecvdGpAdcData_t
Sensors GPADC measurement data for event RL_RF_AE_GPADC_MEAS_DATA_SB.
Definition: mmwavelink.h:2517
rlBssEsmFault_t
Structure to hold the BSS ESM Fault data strucutre for event RL_RF_AE_ESMFAULT_SB.
Definition: mmwavelink.h:1801
rlFwVersionParam_t
mmWaveLink firmware version structure
Definition: mmwavelink.h:2263
rlMssLatentFaultReport_t
Structure to hold the test status report of the latent fault tests data strucutre for event RL_DEV_AE...
Definition: mmwavelink.h:1709
rlComIfCbs_t
Communication interface(SPI, MailBox, UART etc) callback functions.
Definition: mmwavelink.h:900
rlCrcCbs_t
mmWaveLink CRC callback function
Definition: mmwavelink.h:1167
rlCalMonTimingErrorReportData_t
Calibration monitoring timing error data for event RL_RF_AE_MON_TIMING_FAIL_REPORT_SB.
Definition: mmwavelink.h:2581
rlRcvAdcData_t
This async event is in response to the command (RL_DEV_CONFIG_SET_MSG: RL_DEV_RX_DATA_PATH_CONF_SET_S...
Definition: mmwavelink.h:1928
rlMonTempReportData_t
This is the Monitoring report which RadarSS sends to the host, containing the measured temperature ne...
Definition: mmwavelink.h:2693
rlInitComplete_t
mmWaveLink Init Complete data structure for event RL_DEV_AE_MSSPOWERUPDONE_SB
Definition: mmwavelink.h:1393
rlMonPmclkloIntAnaSigRep_t
This is the Monitoring report which RadarSS sends to the host, containing information about Internal ...
Definition: mmwavelink.h:3647
rlMonRxGainPhRep_t
This API is a Monitoring report which RadarSS sends to the host, containing the measured RX gain and ...
Definition: mmwavelink.h:2748
rlMonTxBallBreakRep_t
This is the Monitoring report which RadarSS sends to the host, containing the measured TX reflection ...
Definition: mmwavelink.h:3177
rlMonGpadcIntAnaSigRep_t
This is the Monitoring report which RadarSS sends to the host, containing information about Internal ...
Definition: mmwavelink.h:3704
rlVmonErrStatus_t
This sub block indicates fault in analog supplies or LDO short circuit condition. Once a fault is det...
Definition: mmwavelink.h:1872
rlRfTempData_t
RF characterization Time and Temperature data structure.
Definition: mmwavelink.h:2076
rlOsiSemCbs_t
OS semaphore callback functions.
Definition: mmwavelink.h:1023
rlDeviceCtrlCbs_t
mmWaveLink Device Control, Interrupt callback functions
Definition: mmwavelink.h:1192
rlMonSynthFreqRep_t
This is the Monitoring report which RadarSS sends to the host, containing information related to meas...
Definition: mmwavelink.h:3404
rlTimerCbs_t
mmWaveLink Timer callback functions
Definition: mmwavelink.h:1150
rlDbgCb_t
mmWaveLink debug callback structure
Definition: mmwavelink.h:1305
rlAnalogFaultReportData_t
Analog fault strucure for event RL_RF_AE_ANALOG_FAULT_SB.
Definition: mmwavelink.h:2528
rlMonTxGainPhaMisRep_t
This is the Monitoring report which RadarSS sends to the host, containing the measured Tx gain and ph...
Definition: mmwavelink.h:3219
rlRfApllCalDone_t
API APLL closed loop cal Status Get Sub block structure.
Definition: mmwavelink.h:2052
rlMonTxIntAnaSigRep_t
This is the Monitoring report which RadarSS sends to the host, containing information about Internal ...
Definition: mmwavelink.h:3531
rlMonRxIntAnaSigRep_t
This is the Monitoring report which RadarSS sends to the host, containing information about Internal ...
Definition: mmwavelink.h:3584
rlMssRfErrStatus_t
Structure to hold data strucutre for RF-error status send by MSS for event RL_DEV_AE_MSS_RF_ERROR_STA...
Definition: mmwavelink.h:1780
rlDigLatentFaultReportData_t
Latent fault digital monitoring status data for event RL_RF_AE_DIG_LATENTFAULT_REPORT_AE_SB.
Definition: mmwavelink.h:2602
rlMonPllConVoltRep_t
This is the Monitoring report which RadarSS sends to the host, containing the measured PLL control vo...
Definition: mmwavelink.h:3750
rlGpAdcData_t
GPADC measurement data for sensors.
Definition: mmwavelink.h:2498
rlMonRxMixrInPwrRep_t
This is the Monitoring report which the xWR device sends to the host, containing the measured RX mixe...
Definition: mmwavelink.h:3863
rlMssBootErrStatus_t
Structure to hold the MSS Boot error status data strucutre when booted over SPI for event RL_DEV_AE_M...
Definition: mmwavelink.h:1620
rlMssEsmFault_t
Structure to hold the MSS ESM Fault data strucutre for event RL_DEV_AE_MSS_ESMFAULT_SB.
Definition: mmwavelink.h:1534
rlMonReportHdrData_t
The report header includes common information across all enabled monitors like current FTTI number an...
Definition: mmwavelink.h:2643
rlSwVersionParam_t
mmwavelink software version structure
Definition: mmwavelink.h:2405
rlCmdParserCbs_t
mmWaveLink callback functions for Command parser
Definition: mmwavelink.h:1158
rlOsiMutexCbs_t
OS mutex callback functions.
Definition: mmwavelink.h:963
rlMonExtAnaSigRep_t
This is the Monitoring report which RadarSS sends to the host, containing the external signal voltage...
Definition: mmwavelink.h:3481
rlCpuFault_t
Structure to hold the MSS/radarSS CPU Fault data strucutre for event RL_DEV_AE_MSS_CPUFAULT_SB and RL...
Definition: mmwavelink.h:2130
rlVersion_t
mmwavelink version structure
Definition: mmwavelink.h:2479
rlMssPeriodicTestStatus_t
Structure to hold data strucutre for test status of the periodic tests for event RL_DEV_AE_MSS_PERIOD...
Definition: mmwavelink.h:1759
rlMonTxBpmRep_t
This is the Monitoring report which RadarSS sends to the host, containing the measured TX1 BPM error ...
Definition: mmwavelink.h:3307
rlStartComplete_t
mmWaveLink RF Start Complete data structure for event RL_DEV_AE_RFPOWERUPDONE_SB
Definition: mmwavelink.h:1481
rlEventCbs_t
mmWaveLink Asynchronous event callback function
Definition: mmwavelink.h:1126
rlMonRxIfStageRep_t
This is the Monitoring report which RadarSS sends to the host, containing the measured RX IF filter a...
Definition: mmwavelink.h:2920
rlOsiMsgQCbs_t
OS message queue/Spawn callback functions.
Definition: mmwavelink.h:1083
rlMonTxPowRep_t
This is the Monitoring report which RadarSS sends to the host, containing the measured TX power value...
Definition: mmwavelink.h:3106
rlOsiCbs_t
OS services callback functions.
Definition: mmwavelink.h:1107
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