53 #include <ti/control/mmwavelink/include/rl_protocol.h>    69 #define RL_DEV_I_FIRST                  (0x0U)    70 #define RL_DEV_Q_FIRST                  (0x1U)    71 #define RL_DEV_IQSWAP_MAX               (0x2U)    76 #define RL_DEV_CH_INTERLEAVED           (0x0U)    77 #define RL_DEV_CH_NON_INTERLEAVED       (0x1U)    78 #define RL_DEV_CH_INTERLEAVE_MAX        (0x2U)    84 typedef struct rlFileData
    93     rlUInt16_t fData[RL_CMD_PL_LEN_MAX/2U];
   100 typedef struct rlMcuClkCfg
   102 #ifndef MMWL_BIG_ENDIAN   150     rlUInt8_t mcuClkCtrl;
   172 typedef struct rlPmicClkCfg
   174 #ifndef MMWL_BIG_ENDIAN   221     rlUInt8_t pmicClkSrc;
   228     rlUInt8_t pmicClkCtrl;
   263 #ifndef MMWL_BIG_ENDIAN   293     rlUInt8_t maxNdivVal;
   298     rlUInt8_t minNdivVal;
   312     rlUInt8_t clkDitherEn;
   319 typedef struct rllatentFault
   367 #ifndef MMWL_BIG_ENDIAN   406 typedef struct rlperiodicTest
   419 #ifndef MMWL_BIG_ENDIAN   451 typedef struct rltestPattern
   453 #ifndef MMWL_BIG_ENDIAN   472     rlUInt8_t  testPatGenTime;
   479     rlUInt8_t  testPatGenCtrl;
   585 typedef struct rlDevDataFmtCfg
   611 #ifndef MMWL_BIG_ENDIAN   635     rlUInt8_t chInterleave;
   653 typedef struct rlDevDataPathCfg
   655 #ifndef MMWL_BIG_ENDIAN   743     rlUInt8_t transferFmtPkt0;
   774     rlUInt8_t transferFmtPkt1;
   782     rlUInt8_t cq2TransSize;
   790     rlUInt8_t cq1TransSize;
   802     rlUInt8_t cq0TransSize;
   809 typedef struct rlDevLaneEnable
   837 typedef struct rlDevDataPathClkCfg
   839 #ifndef MMWL_BIG_ENDIAN   876     rlUInt8_t laneClkCfg;
   887 typedef struct rlDevLvdsLaneCfg
   929 typedef struct rlDevContStreamingModeCfg
   944 typedef struct rlDevCsi2Cfg
   998 typedef struct rlDevHsiClk
  1019 typedef struct rlDevHsiCfg
  1035 typedef struct rlDevConfig
  1037 #ifndef MMWL_BIG_ENDIAN  1044     rlUInt8_t aeCrcConfig;
  1048     rlUInt8_t reserved0;
  1053     rlUInt8_t reserved0;
  1060     rlUInt8_t aeCrcConfig;
  1065     rlUInt16_t reserved1;
  1069     rlUInt32_t reserved2;
  1073     rlUInt32_t reserved3;
  1108                                                rlUInt16_t remChunks);
  1149                                                 rlDevMiscCfg_t *data);
  1188 MMWL_EXPORT rlReturnVal_t rlDeviceGetDataPathClkConfig(rlUInt8_t deviceMap,
  1190 MMWL_EXPORT rlReturnVal_t rlDeviceSetLvdsLaneConfig(rlUInt8_t deviceMap,
  1192 MMWL_EXPORT rlReturnVal_t rlDeviceGetLvdsLaneConfig(rlUInt8_t deviceMap,
 rlUInt8_t transferFmtPkt0
Data out Format,   b5:0 Packet 0 content selection   000001 - ADC_DATA_ONLY   000110 - CP_ADC_DATA   ...
MMWL_EXPORT rlReturnVal_t rlDevicePmicClkConfig(rlUInt8_t deviceMap, rlPmicClkCfg_t *data)
Sets the configurations for PMIC clock. 
rlUInt16_t reserved
Reserved for future use  . 
MMWL_EXPORT rlReturnVal_t rlDeviceSetDataFmtConfig(rlUInt8_t deviceMap, rlDevDataFmtCfg_t *data)
Sets LVDS/CSI2 Data output format. 
rlUInt8_t mcuClkSrc
This field specifies the source of the MCU clock. Applicable only in case of MCU   clock enable...
MMWL_EXPORT rlReturnVal_t rlDeviceRfStart(rlUInt8_t deviceMap)
Enables mmwave RF/Analog Sub system. 
mmWaveLink client callback structure 
rlUInt16_t testPatrnPktSize
Number of ADC samples to capture for each RX Valid range: 64 to MAX_NUM_SAMPLES, Where MAX_NUM_SAMPLE...
rlUInt32_t reserved1
Reserved for future use. 
rlUInt32_t reserved
Reserved for future use. 
rlUInt16_t contStreamModeEn
Enable - 1, Disable - 0. 
MMWL_EXPORT rlReturnVal_t rlDeviceMcuClkConfig(rlUInt8_t deviceMap, rlMcuClkCfg_t *data)
Sets the configurations to setup the desired frequency of the MCU Clock. 
rlUInt32_t freqSlope
Applicable only in case of PMIC clock enable. Else ignored.   Bit[25:0] - Frequency slope value to be...
rlUInt32_t testPatRx1Qcfg
This field specifies the values for Rx1, Q channel.   Applicable only in case of test pattern enable...
rlUInt32_t lanePosPolSel
b2:0 - DATA_LANE0_POS   Valid values (Should be a unique position if lane 0 is enabled, ignored if   lane 0 is not enabled):   000b - Unused, 001b - Position 1 (default),   010b - Position 2, 011b - Position 3,   100b - Position 4, 101b - Position 5   b3 DATA_LANE0_POL   0b - PLUSMINUS pin order, 1b - MINUSPLUS pin order   b6:4 DATA_LANE1_POS   Valid values (Should be a unique position if lane 1 is   enabled, ignored if lane 1 is not enabled):   000b - Unused, 001b - Position 1,   010b - Position 2 (default), 011b - Position 3,   100b - Position 4, 101b - Position 5   b7 DATA_LANE1_POL   0b - PLUSMINUS pin order, 1b - MINUSPLUS pin order   b10:8 DATA_LANE2_POS   Valid values (Should be a unique position if lane 2 is   enabled, ignored if lane 2 is not enabled):   000b - Unused, 001b - Position 1,   010b - Position 2, 011b - Position 3,   100b - Position 4 (default), 101b - Position 5   b11 DATA_LANE2_POL   0b - PLUSMINUS pin order, 1b - MINUSPLUS pin order   b14:12 DATA_LANE3_POS   Valid values (Should be a unique position if lane 3 is   enabled, ignored if lane 3 is not enabled):   000b - Unused, 001b - Position 1,   010b - Position 2, 011b - Position 3,   100b - Position 4, 101b - Position 5 (default)   b15 DATA_LANE3_POL   0b - PLUSMINUS pin order, 1b - MINUSPLUS pin order   b18:16 CLOCK_POS   Valid values (Should be a unique position):   001b - Position 1,   010b - Position 2, 011b - Position 3 (default),   100b - Position 4   b19 CLOCK_POL   0b - PLUSMINUS pin order, 1b - MINUSPLUS pin order   b31:20 RESERVED  
MMWL_EXPORT rlReturnVal_t rlDeviceGetCsi2Config(rlUInt8_t deviceMap, rlDevCsi2Cfg_t *data)
Gets Csi2 data format Configuration. 
MMWL_EXPORT rlReturnVal_t rlDeviceLatentFaultTests(rlUInt8_t deviceMap, rllatentFault_t *data)
Sets the configurations for latent fault test. 
mmWaveLink firmware version structure 
MMWL_EXPORT rlReturnVal_t rlDeviceGetMmWaveLinkVersion(rlSwVersionParam_t *data)
Get mmWaveLink Version. 
MMWL_EXPORT rlReturnVal_t rlDeviceSetTestPatternConfig(rlUInt8_t deviceMap, rltestPattern_t *data)
Setup for test pattern to be generated. 
MMWL_EXPORT rlReturnVal_t rlDeviceSetDataPathClkConfig(rlUInt8_t deviceMap, rlDevDataPathClkCfg_t *data)
Sets LVDS Clock Configuration. 
rlUInt8_t chInterleave
Channel interleaving of the samples stored in   the ADC buffer to be transferred out on the data path...
rlUInt8_t srcClkDiv
This field specifies the division factor to be applie to source clock.   Applicable only in case of P...
MMWL_EXPORT rlReturnVal_t rlDeviceSetContStreamingModeConfig(rlUInt8_t deviceMap, rlDevContStreamingModeCfg_t *data)
Sets Continous Streaming Mode Configuration. 
MMWL_EXPORT rlReturnVal_t rlDeviceRemoveDevices(rlUInt8_t deviceMap)
Removes connected mmwave devices. 
rlUInt8_t reserved
Reserved for future use. 
rlDevDataPathCfg_t * dataPath
Data path config. 
rlUInt16_t reserved
Reserved for future use. 
rlUInt16_t rxChannelEn
RX Channel Bitmap   b0 RX0 Channel Enable   0 Disable RX Channel 0   1 Enable RX Channel 0   b1 RX1 C...
mmwave radar data path config. 
MMWL_EXPORT rlReturnVal_t rlDeviceSetHsiClk(rlUInt8_t deviceMap, rlDevHsiClk_t *data)
Sets High Speed Interface Clock. 
rlUInt32_t testPatRx2Icfg
This field specifies the values for Rx2, I channel.   Applicable only in case of test pattern enable...
Continous streaming mode configuration. 
rlUInt16_t laneParamCfg
Lane Parameter configurations   b0 - 0(LSB first), 1(MSB first)   b1 - 0(Packet End Pulse Disable)...
MMWL_EXPORT rlReturnVal_t rlDeviceEnablePeriodicTests(rlUInt8_t deviceMap, rlperiodicTest_t *data)
Sets the configurations for periodic test. 
mmwave radar high speed Data path configuraiton 
DataPath clock configuration. 
mmwave radar high speed clock configuration 
mmwave radar device latent fault test 
rlUInt32_t testEn1
Bits Definition   0 MibSPI self-test   1 DMA self-test   2 RESERVED   3 RTI self-test   4 ESM self-te...
rlUInt8_t cq0TransSize
Number of samples (in 16 bit halfwords) of CQ0 data to be transferred. Valid range [32 halfwords to 1...
rlUInt8_t intfSel
Data Path Interface,   0x0 CSI2 interface selected   0x1 LVDS interface selected   0x2 SPI interface ...
rlUInt16_t adcFmt
ADC out format - 0(Real), 1(Complex), 2(Complex with Image band), 3(Pseudo Real) 
MMWL_EXPORT rlReturnVal_t rlDeviceGetRfVersion(rlUInt8_t deviceMap, rlFwVersionParam_t *data)
Get mmWave RF ROM and patch version. 
MMWL_EXPORT rlReturnVal_t rlDeviceGetMssVersion(rlUInt8_t deviceMap, rlFwVersionParam_t *data)
Get mmWave Master SS version. 
rlUInt32_t testPatRx3Icfg
This field specifies the values for Rx3, I channel.   Applicable only in case of test pattern enable...
rlUInt16_t reserved
Reserved for future use. 
rlUInt16_t reserved1
Reserved for future use. 
rlUInt8_t reserved
Reserved for future use. 
rlUInt16_t laneFmtMap
Lane format   0x0000 Format map 0 (Rx0,Rx1,...)   0x0001 Format map 1 (Rx3,Rx2,...)  . 
rlUInt8_t repMode
Value Definition   0 Report is sent every monitoring period   1 Report is sent only on a failure  ...
MMWL_EXPORT rlReturnVal_t rlDeviceFileDownload(rlUInt8_t deviceMap, rlFileData_t *data, rlUInt16_t remChunks)
Download mmwave Firmware/Patches over SPI. 
mmwave radar test pattern config 
rlUInt8_t testMode
Value Definition   0 Production mode. Latent faults are tested and any failures are reported   1 Char...
rlUInt32_t testEn2
Bits Definition   0 DCC self test   1 DCC fault insertion   2 PCR fault generation test   3 VIM RAM p...
rlUInt8_t dataRate
Data rate selection   0000b - 900 Mbps (DDR only)   0001b - 600 Mbps (DDR only)   0010b - 450 Mbps (S...
rlUInt8_t modeSel
This field specifies the mode of operation for the PMIC clock generation.   Applicable only in case o...
rlUInt32_t numTestPtrnPkts
Number of test pattern packets to send, for infinite packets set it to 0. 
rlDevDataPathClkCfg_t * dataPathClk
Data path clock configuration. 
rlUInt32_t periodicity
1 LSB = 1 ms Periodicity at which tests need to be run 
rlUInt32_t reserved
Reserved for future use. 
rlUInt8_t iqSwapSel
I/Q Swap selection for complex outputs   0 Sample interleave mode - I first   1 Sample interleave mod...
MMWL_EXPORT rlReturnVal_t rlDeviceConfigureAckTimeout(rlUInt32_t ackTimeout)
Configures the Acknowledgement timeout in mmWaveLink Driver. 
mmwave radar data path lane enable 
MMWL_EXPORT rlReturnVal_t rlDeviceSetLaneConfig(rlUInt8_t deviceMap, rlDevLaneEnable_t *data)
Sets Lane enable Configuration. 
rlUInt8_t cq1TransSize
Number of samples (in 16 bit halfwords) of CQ1 data to be transferred. Valid range [32 halfwords to 1...
rlUInt32_t testPatRx0Qcfg
This field specifies the values for Rx0, Q channel. Applicable only in case of   test pattern enable...
rlUInt8_t testPatGenCtrl
This field controls the enable-disable of the generation of the test pattern.   Value Description   0...
MMWL_EXPORT rlReturnVal_t rlDeviceGetDataPathConfig(rlUInt8_t deviceMap, rlDevDataPathCfg_t *data)
Gets data path Configuration. 
MMWL_EXPORT rlReturnVal_t rlDeviceSetHsiConfig(rlUInt8_t deviceMap, rlDevHsiCfg_t *data)
: This function sets the High Speed Interface(LVDS/CSI2) clock, lane, data rate and data format ...
mmwave radar periodicity test config 
MMWL_EXPORT rlReturnVal_t rlDeviceSetCsi2Config(rlUInt8_t deviceMap, rlDevCsi2Cfg_t *data)
Sets CSI2 data format Configuration. 
rlUInt32_t testPatRx3Qcfg
This field specifies the values for Rx3, Q channel.   Applicable only in case of test pattern enable...
rlUInt8_t reserved
Reserved for future use. 
rlUInt32_t chunkLen
File data length. 
mmwave radar data format config 
mmwave radar device MCU Clock output 
rlUInt8_t testPatGenTime
Number of system clocks (200 MHz) between successive samples for the test pattern   gen...
mmwave radar device PMIC Clock output 
rlUInt32_t testPatRx0Icfg
This field specifies the values for Rx0, I channel. Applicable only in case of   test pattern enable...
rlUInt16_t reserved
Reserved for future use. 
MMWL_EXPORT rlReturnVal_t rlDeviceSetMiscConfig(rlUInt8_t deviceMap, rlDevMiscCfg_t *data)
Setup misc. device configurations. 
MMWL_EXPORT rlReturnVal_t rlDevicePowerOn(rlUInt8_t deviceMap, rlClientCbs_t clientCb)
Bring mmwave Device Out of Reset. 
rlUInt8_t transferFmtPkt1
Data out Format,   b5:0 Packet 1 content selection   000000 - Suppress Packet 1   001110 - CP_CQ_DATA...
rlUInt8_t minNdivVal
Applicable only in case of PMIC clock enable. Else ignored. Min allowed divider   value (depends upon...
rlUInt32_t testEn
Bit value definition: 1 - Enable, 0 - Disable   Bit Monitoring type   0 PERIODIC_CONFG_REGISTER_READ_...
rlUInt8_t cqConfig
This field specifies the data size of CQ samples on the lanes.   b1:0 Data size   00 12 bits   01 14 ...
mmwavelink software version structure 
rlUInt8_t repMode
Value Definition   0 Report is sent after test completion   1 Report is send only upon a failure  ...
rlUInt32_t testPatRx2Qcfg
This field specifies the values for Rx2, Q channel.   Applicable only in case of test pattern enable...
MMWL_EXPORT rlReturnVal_t rlDevicePowerOff(void)
Shutdown mmwave Device. 
rlUInt8_t pmicClkCtrl
This field controls the enable - disable of the PMIC clock.   Value Description   0x0 Disable PMIC cl...
rlUInt32_t testPatRx1Icfg
This field specifies the values for Rx1, I channel. Applicable only in case of   test pattern enable...
File Dowload data structure. 
rlUInt16_t reserved
Reserved for future use. 
rlUInt16_t laneEn
Lane Enable Bitmap   b0 Lane 0 Enable   0 Disable lane 0   1 Enable lane 0   b1 Lane 1 Enable   0 Dis...
rlUInt8_t laneClkCfg
Clock COnfiguration   0 -SDR Clock   1 - DDR Clock (Only valid value for CSI2)  . ...
mmwavelink version structure 
rlUInt16_t adcBits
ADC out bits - 0(12 Bits), 1(14 Bits), 2(16 Bits) 
rlUInt8_t srcClkDiv
This field specifies the division factor to be applied to source clock.   Applicable only in case of ...
MMWL_EXPORT rlReturnVal_t rlDeviceSetDataPathConfig(rlUInt8_t deviceMap, rlDevDataPathCfg_t *data)
Sets LVDS/CSI2 Path Configuration. 
MMWL_EXPORT rlReturnVal_t rlDeviceGetContStreamingModeConfig(rlUInt8_t deviceMap, rlDevContStreamingModeCfg_t *data)
Gets continuous Streaming Mode Configuration. 
MMWL_EXPORT rlReturnVal_t rlDeviceGetDataFmtConfig(rlUInt8_t deviceMap, rlDevDataFmtCfg_t *data)
Gets LVDS/CSI2 Data output format. 
rlUInt8_t maxNdivVal
Applicable only in case of PMIC clock enable. Else ignored. Max allowed divider   value (depends upon...
MMWL_EXPORT rlReturnVal_t rlDeviceConfigureCrc(rlCrcType_t crcType)
Configures the CRC Type in mmWaveLink Driver. 
rlUInt8_t reserved0
Reserved for future use. 
rlUInt16_t hsiClk
High Speed Interface Clock configurations. Below table indicates possible values for different data r...
rlUInt8_t mcuClkCtrl
This field controls the enable - disable of the MCU clock.   Value Description   0x0 Disable MCU cloc...
rlUInt8_t cq2TransSize
Number of samples (in 16 bit halfwords) of CQ2 data to be transferred. Valid range [32 halfwords to 1...
MMWL_EXPORT rlReturnVal_t rlDeviceAddDevices(rlUInt8_t deviceMap)
Bring mmwave Device Out of Reset. 
MMWL_EXPORT rlReturnVal_t rlDeviceGetLaneConfig(rlUInt8_t deviceMap, rlDevLaneEnable_t *data)
Gets Lane enable Configuration. 
rlDevDataFmtCfg_t * datafmt
Data format config. 
rlUInt8_t pmicClkSrc
This field specifies the source of the PMIC clock. Applicable only in case of   PMIC clock enable...
rlUInt8_t clkDitherEn
Applicable only in case of PMIC clock enable. Else ignored. This field controls   the enable-disable ...
MMWL_EXPORT rlReturnVal_t rlDeviceGetVersion(rlUInt8_t deviceMap, rlVersion_t *data)
Get mmWave Hardware, Firmware/patch and mmWaveLink version.